74HC165D,653 vs 74HC165D,652 Comparison
Detailed side-by-side comparison of 74HC165D,653 by Nexperia and 74HC165D,652 by Nexperia. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Nexperia
74HC165D,653 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,653 ✓ ActiveNexperia
74HC165D,652 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,652 ✓ ActiveSpecification Comparison
| Parameter | 74HC165D,653 | 74HC165D,652 |
|---|---|---|
| Brand | Nexperia | Nexperia |
| Category | Logic ICs | Logic ICs |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.15 | $0.16 |
| Logic Type | Shift Register (Parallel-in/Serial-out) | Shift Register |
| Function | Parallel or Serial to Serial | Parallel or Serial to Serial |
| Number of Elements | 1 | 1 |
| Number of Bits per Element | 8 | 8 |
| Output Type | Differential (Q7 and Q7-bar complementary outputs) | Differential (complementary Q7 and Q7-bar) |
| Supply Voltage (VCC) | 2 V to 6 V | 2 V to 6 V |
| Input Voltage | 0 V to VCC | — |
| Output Drive (IO) | ±5.2 mA | — |
| Propagation Delay (tpd) | 6 ns typical at VCC = 5 V, CL = 50 pF [DATA_NEEDED: explicit propagation delay value] | — |
| Operating Temperature | -40 C to +125 C | -40 °C to +125 °C |
| Package | 16-pin SOIC (SOT109-1) | 16-SOIC (SOT109-1), 0.154" (3.90 mm) width |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | 1 (per JEDEC J-STD-020) | — |
| RoHS Status | Compliant | Compliant |
| JEDEC Compliance | JESD7A (per datasheet) | — |
| Pin Compatibility | LSTTL 74LS165 | — |
| Technology | High-speed Si-gate CMOS | — |
| Logic Family | — | 74HC (high-speed Si-gate CMOS) |
| Input Type | — | CMOS (HC); pin-compatible with TTL/LSTTL |
| Number of Pins | — | 16 |
| Standard Compliance | — | JEDEC standard no. 7A |
| Pin Compatible With | — | Low-power Schottky TTL (LSTTL) |
| Parallel Load | — | Asynchronous via SH/LD-bar |
| Serial Data Input | — | DS (for daisy-chaining) |
| Clock Input | — | CP (rising-edge triggered) with clock inhibit (CE-bar) |