74HC165D,652 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
MPN: 74HC165D,652 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.42 | $0.42 |
| 10 | $0.36 | $3.60 |
| 100 | $0.27 | $27.00 |
| 500 | $0.22 | $110.00 |
| 1,000 | $0.18 | $180.00 |
| 2,500 | $0.16 | $400.00 |
74HC165D,652 Overview
A shift register is a sequential logic device that converts between serial and parallel data formats, sitting in the broader hierarchy of digital logic ICs, specifically the registers, latches, and counters category. The 74HC family uses silicon-gate CMOS technology to deliver TTL-compatible logic levels with substantially lower power consumption than bipolar LSTTL, making it the industry workhorse for glue logic, I/O expansion, and display/keypad scanning subsystems where a microcontroller lacks sufficient native GPIO pins.
Key features include a wide 2 V to 6 V operating supply, asynchronous parallel load via the SH/LD-bar pin, clock inhibit input, complementary Q7/Q7-bar outputs for cascading, and serial data input (DS) for daisy-chaining multiple devices. The HC variant provides CMOS input switching levels with low quiescent current, and the part is specified from -40 °C to +125 °C across the industrial operating range. Propagation delays are typically in the low tens of nanoseconds at 6 V, sufficient for MCU-driven peripheral scanning at hundreds of kilohertz.
The device uses a master shift register plus a parallel load register architecture controlled by SH/LD-bar. When SH/LD-bar is LOW, the asynchronous parallel inputs D0-D7 are clocked into the shift register; when HIGH, the device shifts serial data on each rising edge of the clock. The complementary Q7 and Q7-bar outputs enable direct cascading without external inverters, simplifying design of multi-byte shift chains.
Typical applications include microcontroller I/O expansion, keypad scanning matrices, LED driver multiplexing, input multiplexing for analog signals, and reading multi-position DIP switches or rotary encoders. The parallel-load capability makes it especially useful when many inputs must be sampled simultaneously rather than sequentially.
When designing with this part, place 0.1 µF decoupling close to VCC and observe CMOS static-discharge handling because the parallel data inputs and clock pins are sensitive to ESD. Ensure that SH/LD-bar timing meets the minimum pulse-width specification in the manufacturer datasheet to avoid corrupted parallel loads.
This page consolidates verified distributor pricing, drop-in SOIC-16 alternatives, application notes, and design guidance for the 74HC165D,652 that engineers typically piece together from multiple sources.
Drop-in alternatives for 74HC165D,652 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 74HC165D,652 (same form factor and footprint) — differing in Logic Type, Output Type, Function, Operating Temperature, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
74HC165D,653
✅ Drop-In✓ In Stock
$0.15 / Unit
View Datasheet →74HC165D-Q100,118
✅ Drop-In📋 Reference alternative (not in catalog)
MC74HC165ADR2G
✅ Drop-In📋 Reference alternative (not in catalog)
CD74HC165M96
✅ Drop-In📋 Reference alternative (not in catalog)
SN74HC165DR
✅ Drop-In📋 Reference alternative (not in catalog)
74HCT165D,652
✅ Drop-In📋 Reference alternative (not in catalog)
74HC165D,652 Maximum Ratings & Electrical Characteristics
| Logic Type | Shift Register |
| Function | Parallel or Serial to Serial |
| Number of Elements | 1 |
| Number of Bits per Element | 8 |
| Output Type | Differential (complementary Q7 and Q7-bar) |
| Supply Voltage (VCC) | 2 V to 6 V |
| Logic Family | 74HC (high-speed Si-gate CMOS) |
| Input Type | CMOS (HC); pin-compatible with TTL/LSTTL |
| Operating Temperature | -40 °C to +125 °C |
| Package | 16-SOIC (SOT109-1), 0.154" (3.90 mm) width |
| Mounting Type | Surface Mount |
| Number of Pins | 16 |
| Standard Compliance | JEDEC standard no. 7A |
| Pin Compatible With | Low-power Schottky TTL (LSTTL) |
| Parallel Load | Asynchronous via SH/LD-bar |
| Serial Data Input | DS (for daisy-chaining) |
| Clock Input | CP (rising-edge triggered) with clock inhibit (CE-bar) |
| RoHS Status | Compliant |
74HC165D,652 Pin Configuration
| Pin 1 | SH/LD-bar — Shift/Load input (active LOW: parallel load; HIGH: serial shift) |
| Pin 2 | CP — Clock input (rising-edge triggered) |
| Pin 3 | D4 — Parallel data input 4 |
| Pin 4 | D5 — Parallel data input 5 |
| Pin 5 | D6 — Parallel data input 6 |
| Pin 6 | D7 — Parallel data input 7 |
| Pin 7 | Q7-bar — Complementary serial output |
| Pin 8 | GND — Ground (0 V) |
| Pin 9 | Q7 — Serial output (true) |
| Pin 10 | DS — Serial data input (for cascading) |
| Pin 11 | D0 — Parallel data input 0 (LSB) |
| Pin 12 | D1 — Parallel data input 1 |
| Pin 13 | D2 — Parallel data input 2 |
| Pin 14 | D3 — Parallel data input 3 |
| Pin 15 | CE-bar — Clock enable input (active LOW) |
| Pin 16 | VCC — Positive supply (2 V to 6 V) |
Typical Applications
74HC165D,652 is suitable for 6 applications: Microcontroller GPIO Expansion, Keypad and Switch Matrix Scanning, DIP Switch and Rotary Encoder Input Multiplexing, Industrial Control and PLC Digital Input Cards, Automotive Dashboard Button and Status Panels, Display and LED Driver Multiplexing Front-End.
Microcontroller GPIO Expansion
The 74HC165D,652 is a near-universal solution for expanding microcontroller GPIO when only a few pins remain free, reading up to 8 digital inputs through just 3 MCU pins (CP clock, SH/LD-bar, and Q7 serial data). Its 2-6V VCC range directly interfaces to 3.3V and 5V MCUs without level shifters. The complementary Q7/Q7-bar outputs enable cascading without external inverters, so two 74HC165D,652 chips read 16 inputs using the same 3 MCU pins. Compared to I/O expander ICs over I2C/SPI, this part avoids any protocol overhead and works with bare-metal MCUs and any GPIO capability. Engineers typically pair it with a small microcontroller for keypad or switch-matrix scanning where deterministic timing matters more than wire count.
Recommended
Keypad and Switch Matrix Scanning
For 4x4 or 8x8 matrix keypads, the 74HC165D,652 reads an entire row of switches asynchronously and serially streams the result back to the MCU in a single SH/LD-bar pulse followed by 8 clocks. With complementary Q7 outputs, two devices can share a single MCU clock line and return 16 bits per scan cycle at MHz clock speeds. This eliminates the need for a diode matrix in many designs and supports debouncing entirely in firmware. Operating from -40 °C to +125 °C, the 74HC165D,652 suits industrial HMI panels where keypads must survive wide temperature swings. The 2-6V VCC range also matches battery-powered handheld scanners that run directly from a 3V coin cell.
Recommended
DIP Switch and Rotary Encoder Input Multiplexing
Industrial front panels often combine 8-position DIP switches with rotary encoders and configuration jumpers, easily exceeding the available MCU GPIOs. The 74HC165D,652 reads an entire bank of 8 DIP switches in a single SH/LD-bar pulse, freeing MCU pins for higher-priority analog or PWM functions. Its CMOS-input hysteresis at 5V VCC rejects switch contact bounce noise that would otherwise corrupt I/O readings. The SOIC-16 (SOT109-1) package drops onto the same panel-routing footprints as TI's CD74HC165M, making panel re-spin straightforward. With JEDEC-standard 7A compliance, ESD handling is consistent across vendors.
Recommended
Industrial Control and PLC Digital Input Cards
In PLC digital input modules and industrial sensor aggregation blocks, the 74HC165D,652 reads 8 channelized 24V-to-5V isolated inputs through a single SPI-like scan sequence, dramatically reducing opto-isolator pin count. Its 2-6V supply range simplifies post-isolator 5V regulation, and the wide -40 °C to +125 °C operating range supports outdoor cabinets and factory-floor enclosures. The complementary Q7/Q7-bar outputs simplify multi-card daisy-chaining inside a single PLC backplane. Engineers routinely combine the 74HC165D,652 with TVS diodes and 74HC14 Schmitt triggers for IEC 61131-2 compliant 24V digital input modules.
Recommended
Automotive Dashboard Button and Status Panels
The automotive-grade 74HC165D-Q100,118 variant (same die and SOIC-16 footprint as 74HC165D,652) reads dashboard pushbuttons, HVAC controls, and door-status switches through a single serial stream to the body-control MCU. AEC-Q100 qualification supports under-hood and cabin temperature profiles from -40 °C to +125 °C, and JEDEC standard 7A compliance guarantees consistent ESD behavior. The complementary Q7 outputs enable cascading so a single SPI-style interface handles 16 or 24 buttons per panel. This topology avoids the wire harness complexity of direct GPIO-per-button wiring and simplifies EMC-compliant cable routing.
Recommended
Display and LED Driver Multiplexing Front-End
Large LED matrix displays and seven-segment panels need to read button rows or sensor inputs alongside driving pixels, and the 74HC165D,652 handles the input side without consuming additional MCU pins. Operating at 2-6V VCC, it pairs with common 3.3V LED drivers and 5V legacy display controllers without level translation. With propagation delays around 15 ns at 5V VCC, the part supports button-scanning rates fast enough for gaming peripherals and audio mixers. Its CMOS input thresholds reject ground bounce on long ribbon-cable harnesses, improving first-pass yield on display PCBAs.
Recommended
Recommended Products Summary
Engineering reference data for 74HC165D,652 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 74HC165D,653 | 74HC165D-Q100,118 | MC74HC165ADR2G | CD74HC165M96 | SN74HC165DR |
|---|---|---|---|---|---|---|
| Brand | Nexperia | Nexperia | Nexperia | onsemi | Texas Instruments | Texas Instruments |
| Package | 16-SOIC (SOT109-1) | 16-SOIC (SOT109-1) - same | 16-SOIC - same | 16-SOIC - same | 16-SOIC - same | 16-SOIC - same |
| Supply Voltage | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V |
| Logic Family | 74HC (CMOS) | 74HC (CMOS) | 74HC (CMOS) | 74HC (CMOS) | CD74HC (CMOS) | SN74HC (CMOS) |
| Automotive Qualified | No (industrial) | No | Yes (AEC-Q100) | No | No | No |
| Complementary Q7/Q7-bar Outputs | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C |
| JEDEC Standard Compliance | JESD 7A | JESD 7A | JESD 7A | JESD 7A | JESD 7A | JESD 7A |
Key Differentiators
- Same-die automotive-grade variant available in identical footprint (vs 74HC165D-Q100,118)
- Pin-compatible cross-brand equivalents from major logic vendors (vs MC74HC165ADR2G (onsemi), CD74HC165M96 (TI), SN74HC165DR (TI))
- Complementary Q7/Q7-bar outputs eliminate external inverters when cascading (vs 74HC164 (SIPO, single serial output))
- Asynchronous parallel load enables deterministic multi-bit sampling (vs Pure SIPO shift registers (e.g., 74HC164))
Design Notes
Place a 0.1 µF ceramic decoupling capacitor as close as physically possible to the VCC pin (pin 16) with a short, wide ground return to pin 8. For multi-device shift-register boards driving heavier output loads, add a bulk 1-10 µF electrolytic near the VCC rail. The 74HC165D,652 draws only microamps of quiescent current but its output drive transitions cause brief VCC droop that can disturb neighboring analog or precision logic without proper decoupling.
Route the CP (clock) and SH/LD-bar traces as short, impedance-controlled lines and avoid running them parallel to switching power or motor traces for more than a few millimeters. The asynchronous SH/LD-bar input is sensitive to glitches; if the SH/LD-bar line is routed through long cables or noisy connectors, add a small RC filter (e.g., 1 kΩ + 100 pF) to debounce spurious edges. When cascading Q7->DS between multiple 74HC165D,652 chips, keep the interconnect under 50 mm to preserve timing margin at maximum clock rates.
A common mistake is forgetting to drive SH/LD-bar LOW before clocking in the parallel data: if SH/LD-bar is left HIGH, the device will interpret any noise on D0-D7 as serial bit-stuffing rather than parallel load. Always pulse SH/LD-bar LOW for at least the datasheet minimum pulse width (typically 20 ns at 5 V) before the first rising CP edge. Another pitfall is leaving unused parallel inputs D0-D7 floating; tie them to VCC or GND to prevent shoot-through currents from floating CMOS gates. Finally, do not assume Q7 and Q7-bar are always available simultaneously: in some package variants Q7-bar is internally bonded to a parallel data pin, so verify the SOT109-1 pinout before assuming both outputs are accessible.
Use a ground plane on the layer immediately beneath the 74HC165D,652 to provide a low-impedance return for the fast output edges. Avoid placing the SOIC-16 over power-plane splits; the resulting return-path discontinuity can cause false clocking on CP during high-dV/dt events. Keep at least 2 mm clearance between the 74HC165D,652 and any inductive components (relays, transformers, inductors) to minimize capacitive coupling. When used near connectors or ESD-exposed interfaces, add TVS protection on each parallel input that exits the enclosure.
Compliance Information
RoHS and REACH compliant per Nexperia product page. The base 74HC165D,652 is not AEC-Q100 qualified; choose 74HC165D-Q100,118 for automotive applications. JEDEC standard no. 7A compliance applies. Halogen-free per Nexperia packaging data.
