A42MX36-2BGG272 vs A42MX36-3BGG272 Comparison
Detailed side-by-side comparison of A42MX36-2BGG272 by Microchip Technology and A42MX36-3BGG272 by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
A42MX36-2BGG272 - 54K Gate 5V FPGA, 202 I/O | Microchip
A42MX36-2BGG272 ✓ ActiveMicrochip Technology
A42MX36-3BGG272 - 54K Gate 5V FPGA, 272-ball BGA | Microchip
A42MX36-3BGG272 ✓ ActiveSpecification Comparison
| Parameter | A42MX36-2BGG272 | A42MX36-3BGG272 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $328.25 |
| Family | 42MX (MX FPGA) | MX (42MX) |
| Equivalent Gates | 54,000 | — |
| Configurable Logic Blocks (CLBs) | 1184 | — |
| Logic Cells | 2438 | — |
| User I/O | 202 | — |
| Speed Grade | -2 | -3 |
| Maximum Clock Frequency | 91 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| Programmability | One-Time Programmable (antifuse) | — |
| Embedded Memory | Dual-port SRAM blocks (FIFO/LIFO) | — |
| Package | 272-BBGA | 272-ball BGA (BGG272) |
| Ball Pitch | 1.27 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| JESD-30 Package Code | S-PBGA-B272 | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range for this speed grade suffix] |
| Design Software | Microsemi Designer / ACTgen | — |
| Programmable Type | — | In-System Programmable FPGA |
| Logic Blocks (CLBs) | — | 1184 |
| Equivalent Gate Count | — | 54000 |
| Programmable I/O | — | 202 |
| Combinatorial Delay | — | 1.9 ns |
| Programming Technology | — | Antifuse (one-time programmable) |
| Ceramic/Military Package Option | — | CQ208 / CQ256 screened to MIL-STD-883 (family option) |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |
| Primary Use | — | 5V ASIC alternative / legacy PLD integration |