APA300-FGG256 vs APA300-FG256 Comparison
Detailed side-by-side comparison of APA300-FGG256 by Microchip Technology and APA300-FG256 by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
APA300-FGG256 - 300K ProASICPLUS FPGA | Microchip | Logic
APA300-FGG256 ✓ ActiveMicrochip Technology
APA300-FG256 - ProASICPLUS 300K Gates FPGA, 256-LBGA | Microchip
APA300-FG256 ✓ ActiveSpecification Comparison
| Parameter | APA300-FGG256 | APA300-FG256 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Device Type | ProASICPLUS field-programmable gate array (FPGA) | — |
| Configuration Technology | Flash-based, nonvolatile, reprogrammable configuration | — |
| System Gate Organization | 300,000 gates | — |
| Logic Cells | 8,192 logic cells | — |
| User I/O | 186 I/O | — |
| Maximum Clock Frequency | 180 MHz | — |
| Process Technology | CMOS | — |
| Package Type | 256-terminal square plastic ball grid array (LBGA) | — |
| Terminal Count | 256 terminals | — |
| Ball Pitch | 1.00 mm | — |
| Package Dimensions | 17 x 17 mm | — |
| Seated Height | 2.20 mm | — |
| Temperature Grade | Commercial | — |
| Mounting Type | Surface mount | — |
| RoHS Status | RoHS compliant | Compliant |
| Lead-Free Status | Lead free | — |
| Programmable Logic | Configurable logic, routing, and I/O resources | — |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | 2.5 V |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | 3.3 V (PCI compatible) |
| Operating Temperature Range | [DATA_NEEDED: commercial operating temperature range] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory configuration] | — |
| Family | — | ProASICPLUS (APA300) |
| System Gates | — | 300,000 |
| Logic Cells / Tiles | — | [DATA_NEEDED: tile count] |
| Embedded SRAM | — | 73,728 bits (two-port) |
| User I/Os (max) | — | 186 |
| Package | — | 256-ball LBGA (FG256) |
| Internal Performance | — | up to 350 MHz |
| External Performance | — | up to 150 MHz |
| PCI Support | — | 32-bit, 33 MHz |
| Configuration Method | — | Flash, in-system JTAG (IEEE 1149.1) |
| Live at Power-Up | — | Yes |
| Operating Temperature | — | 0 C to 70 C (commercial) |
| Schmitt Trigger Option | — | Yes (per I/O) |
| Slew-Rate Control | — | Yes (per I/O) |