ATSAMA5D225C-D1M-CUR vs ATSAMA5D28B-CUR Comparison
Detailed side-by-side comparison of ATSAMA5D225C-D1M-CUR by Microchip Technology and ATSAMA5D28B-CUR by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
ATSAMA5D225C-D1M-CUR - ARM Cortex-A5 MPU 500MHz 128Mbit DDR2 | Microchip
ATSAMA5D225C-D1M-CUR ✓ ActiveMicrochip Technology
ATSAMA5D28B-CUR - 500MHz Cortex-A5 MPU 289-LFBGA | Microchip
ATSAMA5D28B-CUR ✓ ActiveSpecification Comparison
| Parameter | ATSAMA5D225C-D1M-CUR | ATSAMA5D28B-CUR |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.80 | $12.60 |
| Family | SAMA5D2 Series | — |
| Core | ARM Cortex-A5 (32-bit, single-core) | — |
| Maximum CPU Clock | 500 MHz | 500 MHz |
| Integrated Memory | 128 Mbit DDR2 SDRAM (16-bit data bus) | — |
| Package | 196-ball TFBGA, 11x11 mm, 0.8 mm pitch | 289-LFBGA (14x14 mm) |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Security | Arm TrustZone, tamper detection, secure boot, secure data storage | — |
| Cryptography | AES, SHA, TRNG hardware accelerators | — |
| Graphics | LCD TFT controller (up to 1024x768) | — |
| Touch Controller | Peripheral Touch Controller (PTC) | — |
| Audio | Embedded audio subsystem with sample-rate converters | — |
| Connectivity | 10/100 Ethernet MAC, USB HS Host/Device, CAN-FD, multiple SPI/I2C/UART | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | Compliant (BGA GREEN) | Compliant |
| Supply Voltage | [DATA_NEEDED: VDD core/IO supply range] | — |
| Boot Media Supported | QSPI NOR, NAND, eMMC, SD card | — |
| Tape & Reel Packaging | Yes (per Mouser listing) | — |
| Core Architecture | — | ARM Cortex-A5 (ARMv7-A) |
| Number of Cores | — | 1 |
| L1 Instruction Cache | — | 32 kbyte |
| L1 Data Cache | — | 32 kbyte |
| L2 Cache / SRAM | — | 128 kbyte (configurable) |
| Memory Management Unit | — | Yes (full MMU) |
| NEON Media Engine | — | Yes (SIMD) |
| Arm TrustZone | — | Yes |
| DRAM Controller | — | LPDDR1/2/3, DDR2/3/3L, 16-bit, with ECC |
| External Bus | — | QSPI |
| Ethernet | — | 10/100 Mbps (1x) |
| USB | — | USB 2.0 + HSIC |
| Operating Temperature | — | -40C to +85C (Industrial) |
| Supply Voltage I/O | — | 3.3 V |