ATSAMD20E15A-AN vs ATSAMD10D14A-SSNT Comparison
Detailed side-by-side comparison of ATSAMD20E15A-AN by Microchip Technology and ATSAMD10D14A-SSNT by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
ATSAMD20E15A-AN - 32KB Flash ARM Cortex-M0+ MCU | Microchip
ATSAMD20E15A-AN β ActiveMicrochip Technology
ATSAMD10D14A-SSNT - 48MHz Cortex-M0+ MCU 16KB Flash | Microchip
ATSAMD10D14A-SSNT β ActiveSpecification Comparison
| Parameter | ATSAMD20E15A-AN | ATSAMD10D14A-SSNT |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1.55 | $1.36 |
| Core Architecture | ARM Cortex-M0+ (32-bit) | β |
| Maximum Clock Frequency | 48 MHz | β |
| Flash Memory | 32 KB | β |
| SRAM | 4 KB | 4 KB |
| Supply Voltage Range | 1.62 V to 3.63 V | β |
| Operating Temperature | -40 C to +105 C | -40C to +105C |
| CoreMark Performance | 2.14 CoreMark/MHz | β |
| ADC Resolution | 12-bit | β |
| DAC Resolution | 10-bit | β |
| Peripheral Touch Controller | 256 channels | β |
| SERCOM Modules | 6 (configurable UART/SPI/I2C) | 6 (configurable as I2C / SPI / UART) |
| Package | 32-pin TQFP | 20-pin SOIC (300 mil) |
| Mounting Type | Surface Mount | β |
| RoHS Status | Compliant | Compliant (per Microchip product page) |
| Lead Free | Yes | β |
| Core | β | ARM Cortex-M0+ (32-bit) |
| Maximum CPU Frequency | β | 48 MHz |
| CoreMark/MHz | β | 2.46 |
| Program Flash Memory | β | 16 KB (16K x 8) |
| Supply Voltage (VDD) | β | 1.6 V to 3.6 V |
| GPIO Pins | β | 14 (max, package-dependent) |
| ADC | β | 12-bit SAR, up to 350 kSps, up to 12 channels |
| Timer / Counter | β | 16-bit TCC and TC peripherals |
| PTC (Touch) | β | Peripheral Touch Controller supported |
| Debug Interface | β | Serial Wire Debug (SWD), 2-wire |
| MSL Level | β | 1 (per SOIC handling guidelines) |