EP1810JM-45 vs EP1810GM883 Comparison
Detailed side-by-side comparison of EP1810JM-45 by Altera and EP1810GM883 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810JM-45 | EP1810GM883 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.20 | $175.00 |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns (max) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | — |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | — |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Pin Count | 68 | — |
| Operating Temperature | -55 C to +125 C (military grade) | -55C to +125C (MIL-STD-883 Class B) |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Mounting Type | Surface Mount (J-lead) | Through-Hole (PGA socket) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| RoHS Status | [DATA_NEEDED: RoHS status - legacy mil-spec part] | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Family | — | Classic EPLD (EP1810 series) |
| Device Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Supply Voltage (Vcc) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Process Technology | — | CMOS, UV-erasable |
| Package | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |