EP1810JM-45 vs EP1810GM883 Comparaison
Comparaison détaillée côte à côte de EP1810JM-45 par Altera et EP1810GM883 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810JM-45 | EP1810GM883 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $14,20 | $175,00 |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns (max) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | — |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | — |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Nombre de broches | 68 | — |
| Température de fonctionnement | -55 C to +125 C (military grade) | -55C to +125C (MIL-STD-883 Class B) |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Type de montage | Surface Mount (J-lead) | Through-Hole (PGA socket) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | Classic EPLD (EP1810 series) |
| Device Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Supply Voltage (Vcc) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Process Technology | — | CMOS, UV-erasable |
| Boîtier | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |