EP1810JM-45 vs EP1810GM883B Comparison

Detailed side-by-side comparison of EP1810JM-45 by Altera and EP1810GM883B by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810JM-45 EP1810GM883B
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Stock Status In Stock In Stock
Unit Price (USD) $14.20 $125.40
Device Family Classic EPLD (EP1810 series) EP1810 (Classic EPLD)
Macrocells 48 48
Usable Gates ~900 gates —
Propagation Delay (tpd) 45 ns (max, -45 speed grade) —
Supply Voltage (VCC) 4.5 V to 5.5 V 4.5 V to 5.5 V
Technology CMOS, UV-EPROM configuration CMOS, UV-erasable
Package Type JLCC-68 (ceramic J-leaded chip carrier) Ceramic Pin Grid Array (PGA), 84 pins
Package Code JM (windowed ceramic, UV-erasable) —
Pin Count 68 —
Operating Temperature -55 C to +125 C (military grade) -55 °C to +125 °C (Military, MIL-STD-883B)
I/O Compatibility CMOS / TTL —
Configuration Method JEDEC fuse map, EPROM programmer —
Programming Technology UV-erasable EPROM (non-volatile, instant-on) —
Mounting Type Surface Mount (J-lead) Through-hole (PGA socket or PCB through-hole)
Logic Type EPLD / PLD (programmable logic device) —
RoHS Status [DATA_NEEDED: RoHS status - legacy mil-spec part] —
MSL Level [DATA_NEEDED: MSL level] —
User Flip-Flops — Up to 64
Total Inputs — 60
Dedicated Inputs — 12
I/O Pins — 48 (bidirectional, tri-state)
Propagation Delay (tPD) — 50 ns max
Package Designator — GM (ceramic PGA)
Processing Level — MIL-STD-883B (Class B)
Programming Method — UV-erasable / Altera programming hardware
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Logic Family — TTL-compatible I/O

Datasheets & Resources

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