EP1810LC-20 vs EP1810LC-35T Comparison
Detailed side-by-side comparison of EP1810LC-20 by Intel and EP1810LC-35T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-20 | EP1810LC-35T |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.85 | $115.20 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | 900 |
| Macrocells | 48 | — |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM | CMOS |
| Programmability | UV-Erasable / OTP | — |
| Dedicated Inputs | 12 | — |
| Package | 68-pin PLCC | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) | T = Tape and Reel |
| Speed Grade | 20 ns (commercial) | — |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| RoHS Status | [DATA_NEEDED: rohs status] | Non-compliant (legacy PLCC product) |
| Device Family | — | EP1810 Classic EPLD |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |