EP1810LC-20 - 900-Gate Classic EPLD, 48 Macrocells, 20ns | Intel
MPN: EP1810LC-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.2 | $4,600.00 |
| 1,000 | $7.85 | $7,850.00 |
Drop-in alternatives for EP1810LC-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810LC-25
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$8.4 / Unit
View Datasheet βEP1810LC-15
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP1810LC-20T
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.95 / Unit
View Datasheet βEP1810LC-30
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.95 / Unit
View Datasheet βEP1810LC-45
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$49.9 / Unit
View Datasheet βEP1810JI-45
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP1810LC-20 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 |
| Macrocells | 48 |
| Maximum Operating Frequency | 50 MHz |
| Propagation Delay (tPD) | 20 ns |
| Supply Voltage | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM |
| Programmability | UV-Erasable / OTP |
| Dedicated Inputs | 12 |
| Package | 68-pin PLCC |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | 20 ns (commercial) |
| Operating Temperature | 0C to +70C (commercial) |
| Mounting Type | Surface Mount |
EP1810LC-20 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 10 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 12 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 13 | INPUT β Dedicated input pin |
| Pin 14 | INPUT β Dedicated input pin |
| Pin 15 | INPUT β Dedicated input pin |
| Pin 16 | INPUT β Dedicated input pin |
| Pin 17 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 18 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 19 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 20 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 21 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 22 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 23 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 24 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 27 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 30 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 34 | INPUT β Dedicated input pin |
| Pin 35 | INPUT β Dedicated input pin |
| Pin 36 | INPUT β Dedicated input pin |
| Pin 37 | INPUT β Dedicated input pin |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 39 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 40 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 41 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 42 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 43 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 44 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 45 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 46 | VCC β +5V supply |
| Pin 47 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 48 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 49 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 50 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 51 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 52 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 53 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 54 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 55 | INPUT β Dedicated input pin |
| Pin 56 | INPUT β Dedicated input pin |
| Pin 57 | INPUT β Dedicated input pin |
| Pin 58 | INPUT β Dedicated input pin |
| Pin 59 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 60 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 61 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 62 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 63 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 64 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 65 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 66 | I/O β Bidirectional I/O pin (macrocell controlled) |
| Pin 67 | GND β Ground |
| Pin 68 | VCC β +5V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-20 is suitable for 6 applications: Legacy 5V Glue Logic Replacement, ISA/VME Bus Address Decoder, Industrial State Machine Controller, Peripheral Interface Controller, Pin-Compatible TTL Replacement, Long-Life-Cycle Military/Avionics Sustaining.
Legacy 5V Glue Logic Replacement
The EP1810LC-20 replaces dense clusters of 74LS/74ALS/74F TTL glue logic with a single non-volatile device, simplifying PCB layout and reducing BOM count in legacy 5V systems. Its 48 macrocells and deterministic 20 ns tPD (Altera Classic datasheet) absorb address decoding, chip-select generation, and bus-control logic that previously required dozens of discrete gates. The 900 usable gates (per Altera spec) consolidate entire decode trees into one PLCC-68 part. Engineers choose this part for long-life-cycle industrial controllers and avionics where the 25+ year production track record outweighs the desire for modern density. Pair with 0.1 uF VCC decoupling placed adjacent to the package and TTL-threshold inputs to preserve noise margin in 5V TTL systems.
Recommended
ISA/VME Bus Address Decoder
In ISA, VME, and similar legacy peripheral buses, the EP1810LC-20 implements the full address-decode and bus-control state machine in a single device. The 12 dedicated inputs and 48 macrocells handle multiple chip-select windows, wait-state insertion logic, and interrupt acknowledge sequencing that previously required multiple PAL/GAL parts. The deterministic 20 ns tPD (Classic family timing model) ensures clean bus arbitration with no metastability surprises versus SRAM-based FPGAs. The 5V supply and TTL-compatible I/O make it directly interface-compatible with bus transceivers like the 74LS245 and 74LS373. Choose this part for industrial backplane designs still shipping today, especially where the design house prefers erasable/OTP logic that can be verified in-circuit.
Recommended
Industrial State Machine Controller
The EP1810LC-20 implements complex sequential controllers for factory automation, motor control, and process equipment where deterministic timing matters more than raw density. Each macrocell's D/T/JK/SR flip-flop plus AND-OR plane allows classic state-machine design patterns with verified setup/hold times from the datasheet. The 50 MHz fMAX supports encoder feedback sampling at high motor RPM, while 5V TTL I/O interfaces directly to industrial sensors, optocouplers, and 24V-to-5V signal conditioners. Non-volatile UV-erasable storage means designs survive power loss with no boot time - critical for safety interlocks. The 0C to +70C commercial grade fits most factory-floor enclosures, and the industrial-temperature EP1810JI-35/EP1810JI-45 variants extend operation to -40C to +85C.
Recommended
Peripheral Interface Controller
The EP1810LC-20 implements Centronics parallel-port emulators, GPIB controllers, SCSI termination logic, and other peripheral interfaces that need glue logic on both host and device sides. The 48 macrocells can encode the full parallel-port state machine plus associated handshake logic in a single device, while the deterministic tCO/tSU timing model lets the engineer guarantee data valid windows without place-and-route iterations. Classic EPLD outputs drive TTL loads directly, simplifying interfaces to 74LS-series transceivers and bus drivers. Although these interfaces are obsolete on modern PCs, they remain ubiquitous in test-and-measurement instruments, industrial printers, and embedded controllers. The Classic part's instant-on behavior (no configuration cycle) is a strong advantage versus SRAM-based FPGAs in production peripherals.
Recommended
Pin-Compatible TTL Replacement
The EP1810LC-20 is widely used as a pin-compatible substitute for aging 74LS/74ALS/74F TTL MSI/LSI parts that have been discontinued. The 20 ns tPD matches the speed of 74LS and 74ALS families, while the integrated macrocell fabric eliminates the proliferation of discrete packages. Engineers designing replacements for end-of-life TTL boards can drop a single 68-pin PLCC onto a footprint-compatible adapter and recover decades of proven logic function. The device is reprogrammable via UV erase (windowed L variant) during development and lockable as OTP for production. This approach is common in military and aerospace sustainment programs that must keep legacy avionics and weapons systems operational.
Recommended
Long-Life-Cycle Military/Avionics Sustaining
Military and aerospace programs (radar systems, avionics computers, communications gear) sustain EP1810LC-20 production because the part appears on legacy bills-of-material that must be supported for 20-30 years. The Classic EPLD's MIL-STD-883B screening (on GM883/GM883B variants) and hermetic package options (GM, GI suffix) make it suitable for high-reliability environments with extended temperature, vibration, and radiation tolerance requirements. The deterministic timing model simplifies DO-254 design assurance for airborne hardware, and the non-volatile EPROM storage means no boot PROM or configuration watchdog is required. Though Intel no longer manufactures new units, sustained-stock and aftermarket inventory is actively broker-traded for these programs. Engineers validate replacement parts against the original datasheet's DC/AC characteristics before installation.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-25 | EP1810LC-15 | EP1810LC-20T | EP1810LC-30 | EP1810LC-45 | EP1810JI-45 |
|---|---|---|---|---|---|---|---|
| Package | 68-pin PLCC | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Propagation Delay (tPD) | 20 ns | 25 ns | 15 ns | 20 ns (same) | 30 ns | 45 ns | 45 ns |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 | 900 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Mid-range 20 ns speed grade balances cost and performance (vs EP1810LC-25)
- Cost-effective versus faster 15 ns speed grade (vs EP1810LC-15)
- Commercial temperature grade vs industrial-temp variants (vs EP1810JI-45)
Design Notes
The EP1810LC-20 requires a single +5V supply (4.75V to 5.25V) with multiple VCC and GND pins distributed around the PLCC-68 package (per the Classic datasheet pinout). Place at least one 0.1 uF ceramic decoupling capacitor adjacent to each VCC/GND pair, and add a bulk 10-47 uF tantalum or low-ESR electrolytic cap near the package to handle the CMOS switching current spikes. ICC is supply-current dependent on fMAX and output loading; estimate 50-100 mA typical for a fully toggling 48-macrocell design. Do not rely on the Classic family's internal power-on reset for sequencing with other logic - add external POR if needed.
The 68-pin PLCC package has 0.050 inch (1.27 mm) pitch J-leads on a square 0.985 inch body. Use a socket if the L (windowed) variant is selected for UV-erase reprogramming during development; otherwise solder directly for production. Route TTL inputs away from noisy clock traces to minimize crosstalk, and keep I/O traces short to reduce ringing on the 5V CMOS outputs. Add 33Ξ© kΞ© series resistors on high-speed outputs if you observe undershoot/overshoot in the prototype. The exposed die (windowed variant) requires a UV-transparent label or socket window if in-circuit erasure is needed.
Common pitfalls when designing with the EP1810LC-20 include: (1) forgetting the 12 dedicated inputs are input-only and cannot be used as outputs - design your pinout accordingly; (2) assuming JTAG or ISP support - the Classic family uses Altera's proprietary programming algorithm via the dedicated programming pins, not JTAG; (3) exceeding the 50 MHz fMAX limit on registered paths - verify with the static timing model; (4) ignoring the OTP/security bit - once programmed and locked, the device cannot be re-read, so always archive the JEDEC fuse map; (5) confusing L (windowed ceramic) vs P (plastic OTP) vs GM (MIL-STD-883B) suffix variants - they have different temperature ranges and reprogrammability. The part is obsolete as of the early 2000s - always check long-term availability before committing to new designs.
Compliance Information
EP1810LC-20 predates RoHS directive (2006). Original Altera production parts are typically non-RoHS; later aftermarket pulls may include RoHS date codes. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. Check Intel product compliance portal for lot-specific MDDS/CoC.
