EP1810LC-30 vs EP1810GC-35 Comparison
Detailed side-by-side comparison of EP1810LC-30 by Altera and EP1810GC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-30 | EP1810GC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $177.12 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | 16 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Supply Voltage | 5 V (typical) | [DATA_NEEDED: VCC range] |
| Technology | CMOS, low-power (LC) | CMOS, UV-erasable EPROM cells |
| Package | JLCC-68 (68-pin J-Lead ceramic chip carrier) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Programming | Device programmer or JTAG | — |
| Operating Temperature | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Number of Pins | 68 | 68 |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS Status | unknown (legacy ceramic package) | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Mounting Type | — | Through Hole |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |