EP1810LC-30 vs EP1810LC-35 Comparison

Detailed side-by-side comparison of EP1810LC-30 by Altera and EP1810LC-35 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ Last Time Buy

Specification Comparison

Parameter EP1810LC-30 EP1810LC-35
Brand Altera Rochester Electronics
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $49.20
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 48 48
Flip-Flops 48 (one per macrocell) —
Speed Grade (tPD) 30 ns —
Supply Voltage 5 V (typical) —
Technology CMOS, low-power (LC) CMOS, UV-erasable EPROM
Package JLCC-68 (68-pin J-Lead ceramic chip carrier) 68-pin PLCC (J-Lead)
Programming Device programmer or JTAG —
Operating Temperature [DATA_NEEDED: temperature grade] 0C to +70C (commercial)
Standby Current [DATA_NEEDED: ICC standby] —
Number of Pins 68 —
Number of I/O Pins [DATA_NEEDED: I/O count] —
Logic Blocks 48 macrocells —
RoHS Status unknown (legacy ceramic package) [DATA_NEEDED]
Device Type — EPLD (Erasable Programmable Logic Device)
Series — Classic EP1810
Equivalent Gates — 900 usable / 2100 equivalent
Maximum Operating Frequency — 28.6 MHz
Propagation Delay (tpd) — 35 ns (max, '-35' speed grade)
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Mounting Type — Surface Mount (socketable)
I/O Pins — [DATA_NEEDED: I/O count exact]
Configuration Method — UV-erase + EPROM programmer
Programmable Interconnect — Centralized Programmable Interconnect Array (PIA)
Development Tool (legacy) — MAX+PLUS II / A+PLUS
Lead-Free — [DATA_NEEDED]

Datasheets & Resources

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