EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
MPN: EP1810LC-35 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $71.16 | $71.16 |
| 10 | $68.5 | $685.00 |
| 100 | $62.4 | $6,240.00 |
| 500 | $55.8 | $27,900.00 |
| 1,000 | $49.2 | $49,200.00 |
Drop-in alternatives for EP1810LC-35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810LC-30
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP1810LC-25
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEP1810LC-20
β Drop-Inβ In Stock
$7.85 / Unit
View Datasheet βEP1810LC-45
β Drop-Inβ In Stock
$49.9 / Unit
View Datasheet βEP1810JC-35
β Drop-Inβ In Stock
$5.48 / Unit
View Datasheet βEP1810JC-45
β Drop-Inβ In Stock
$21.1 / Unit
View Datasheet βEP1810LC-35 Maximum Ratings & Electrical Characteristics
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP1810 |
| Macrocells | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | 28.6 MHz |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM |
| Package | 68-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount (socketable) |
| Operating Temperature | 0C to +70C (commercial) |
| Configuration Method | UV-erase + EPROM programmer |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS |
EP1810LC-35 Pin Configuration
| Pin 1 | I/O β Macrocell I/O pin |
| Pin 2 | I/O β Macrocell I/O pin |
| Pin 3 | I/O β Macrocell I/O pin |
| Pin 4 | I/O β Macrocell I/O pin |
| Pin 5 | I/O β Macrocell I/O pin |
| Pin 6 | I/O β Macrocell I/O pin |
| Pin 7 | I/O β Macrocell I/O pin |
| Pin 8 | I/O β Macrocell I/O pin |
| Pin 9 | I/O β Macrocell I/O pin |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β Macrocell I/O pin |
| Pin 12 | I/O β Macrocell I/O pin |
| Pin 13 | I/O β Macrocell I/O pin |
| Pin 14 | I/O β Macrocell I/O pin |
| Pin 15 | I/O β Macrocell I/O pin |
| Pin 16 | I/O β Macrocell I/O pin |
| Pin 17 | I/O β Macrocell I/O pin |
| Pin 18 | I/O β Macrocell I/O pin |
| Pin 19 | I/O β Macrocell I/O pin |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β Macrocell I/O pin |
| Pin 22 | I/O β Macrocell I/O pin |
| Pin 23 | I/O β Macrocell I/O pin |
| Pin 24 | I/O β Macrocell I/O pin |
| Pin 25 | I/O β Macrocell I/O pin |
| Pin 26 | I/O β Macrocell I/O pin |
| Pin 27 | I/O β Macrocell I/O pin |
| Pin 28 | I/O β Macrocell I/O pin |
| Pin 29 | I/O β Macrocell I/O pin |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β Macrocell I/O pin |
| Pin 32 | I/O β Macrocell I/O pin |
| Pin 33 | I/O β Macrocell I/O pin |
| Pin 34 | I/O β Macrocell I/O pin |
| Pin 35 | I/O β Macrocell I/O pin |
| Pin 36 | I/O β Macrocell I/O pin |
| Pin 37 | I/O β Macrocell I/O pin |
| Pin 38 | I/O β Macrocell I/O pin |
| Pin 39 | I/O β Macrocell I/O pin |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β Macrocell I/O pin |
| Pin 42 | I/O β Macrocell I/O pin |
| Pin 43 | I/O β Macrocell I/O pin |
| Pin 44 | I/O β Macrocell I/O pin |
| Pin 45 | I/O β Macrocell I/O pin |
| Pin 46 | I/O β Macrocell I/O pin |
| Pin 47 | I/O β Macrocell I/O pin |
| Pin 48 | I/O β Macrocell I/O pin |
| Pin 49 | I/O β Macrocell I/O pin |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β Macrocell I/O pin |
| Pin 52 | I/O β Macrocell I/O pin |
| Pin 53 | I/O β Macrocell I/O pin |
| Pin 54 | I/O β Macrocell I/O pin |
| Pin 55 | I/O β Macrocell I/O pin |
| Pin 56 | I/O β Macrocell I/O pin |
| Pin 57 | I/O β Macrocell I/O pin |
| Pin 58 | I/O β Macrocell I/O pin |
| Pin 59 | I/O β Macrocell I/O pin |
| Pin 60 | GND β Ground |
| Pin 61 | VCC β +5V supply |
| Pin 62 | I/O β Macrocell I/O pin |
| Pin 63 | I/O β Macrocell I/O pin |
| Pin 64 | I/O β Macrocell I/O pin |
| Pin 65 | I/O β Macrocell I/O pin |
| Pin 66 | I/O β Macrocell I/O pin |
| Pin 67 | I/O β Macrocell I/O pin |
| Pin 68 | I/O β Macrocell I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-35 is suitable for 6 applications: TTL/MSI Logic Integration (Glue Logic Replacement), Address Decoding and Bus Interface Logic, State Machine and Sequencer Replacement, Legacy Industrial Controller Maintenance, Avionics and Military Legacy Systems, Test Equipment and Instrument Front-End Logic.
TTL/MSI Logic Integration (Glue Logic Replacement)
The EP1810LC-35 is well suited to consolidating multiple 74-series TTL packages (74LS00, 74LS138, 74LS151, etc.) onto a single programmable device. With 48 macrocells delivering ~900 usable gates, the part can replace dozens of discrete SSI/MSI packages on legacy boards. Its 35ns propagation delay preserves the timing margins of the original TTL design, and the 5V CMOS EPROM technology drops quiescent power dramatically compared to bipolar TTL - critical for power-supply-thermal-constrained industrial control cabinets.
Recommended
Address Decoding and Bus Interface Logic
In 80C186, 68k, and Z80-based embedded systems, the EP1810LC-35 functions as a dedicated address decoder and bus-interface controller. Its 48 macrocells are more than sufficient to implement full address-decoder trees, chip-select generation, wait-state insertion, and byte-swapping logic for 16-bit and 32-bit buses. The 35ns tpd fits comfortably within typical bus-access timing budgets of 8-16 MHz microprocessor systems, and the JTAG-compatible boundary-scan support simplifies board-level test.
Recommended
State Machine and Sequencer Replacement
Each EP1810LC-35 macrocell provides a flip-flop with dedicated preset, reset, and clock controls, making the device ideal for implementing complex state machines and sequencers that previously required multiple PAL/GAL devices. Engineers can encode 16-, 24-, or 32-state FSMs plus combinational output decoding in a single EP1810LC-35, eliminating timing skew between state registers. The deterministic PIA-based interconnect guarantees consistent state-machine behavior regardless of logic placement.
Recommended
Legacy Industrial Controller Maintenance
Many industrial controllers, CNC machines, and process-control systems shipped in the 1990s use EP1810-family EPLDs as central glue-logic devices. The EP1810LC-35 is the recommended direct replacement for these legacy systems because Rochester Electronics maintains factory-traceable, electrically-tested inventory that matches the original Altera specifications. Replacing a failed EP1810LC-35 on a 25-year-old PLC board avoids a costly full-system redesign and extends the operating life of installed equipment by another decade.
Recommended
Avionics and Military Legacy Systems
Military and avionics platforms with field-deployed EP1810LC-35 EPLDs require long-life-cycle, factory-traceable replacements. Rochester Electronics specializes in sustaining production of mature Altera Classic parts for these applications, with full MIL-spec traceability. The EP1810LC-35's CMOS EPROM technology provides non-volatile configuration without battery backup - critical for vibration- and temperature-stressed avionics environments where SRAM-based FPGAs are not suitable.
Recommended
Test Equipment and Instrument Front-End Logic
Bench-top test instruments (logic analyzers, protocol analyzers, and pattern generators) from the late 1980s through mid-1990s used EP1810-family EPLDs to implement timing generators, trigger sequencers, and parallel-data formatting. The EP1810LC-35's 35ns tpd and 28.6 MHz maximum clock support the timing budgets of these instruments, while the JTAG boundary-scan simplifies in-system test of the assembled boards. For repair shops, sourcing a Rochester-tested EP1810LC-35 restores instrument calibration and timing accuracy.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-30 | EP1810LC-25 | EP1810LC-20 | EP1810LC-45 | EP1810JC-35 | EP1810JC-45 |
|---|---|---|---|---|---|---|---|
| Brand | Rochester Electronics (originally Altera) | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics |
| Package | 68-pin PLCC (J-Lead) | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same | 68-pin PLCC - same |
| Speed Grade (tpd) | 35 ns | 30 ns (faster) | 25 ns (faster) | 20 ns (faster) | 45 ns (slower) | 35 ns (same) | 45 ns (slower) |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 | 48 |
| Maximum Frequency | 28.6 MHz | ~33 MHz | ~40 MHz | ~50 MHz | ~22 MHz | 28.6 MHz | ~22 MHz |
| Equivalent Gates | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent | 900 usable / 2100 equivalent |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
Key Differentiators
- Better speed grade for legacy designs requiring 28.6 MHz operation (vs EP1810LC-45)
- Slower but lower-cost option for legacy repair only (vs EP1810LC-30)
- Pinout-identical across entire EP1810 family for universal board compatibility (vs EP1810JC-35)
Design Notes
The EP1810LC-35 is NOT supported by modern Altera/Intel Quartus toolchains. Engineers must use the legacy MAX+PLUS II or A+PLUS development environment, which Altera discontinued decades ago. Programming requires a UV-erasable EPROM programmer compatible with the Classic family. For new designs, plan to use a MAX II, MAX V, or MAX 10 CPLD instead - the EP1810LC-35 should be reserved for legacy board repair and obsolescence-management scenarios only.
The EP1810LC-35 is specified for 5V Β±5% operation (4.75V to 5.25V). Operating below 4.75V will cause timing-margin violations and possible logic errors; operating above 5.25V risks permanent CMOS damage. The PLCC-68 package's CMOS EPROM technology draws negligible standby current (microamps), but dynamic current at 28.6 MHz can reach 50-100 mA depending on toggle rate. Decouple VCC with at least one 0.1uF ceramic capacitor per VCC pin, placed within 5mm of the package.
For 68-pin PLCC boards carrying EP1810-family EPLDs, provide a generous ground plane on the component side and stitch the PLCC socket with multiple through-hole vias to the ground plane. The Classic EPLD's PIA-based interconnect is relatively insensitive to signal-integrity issues, but high-speed designs approaching 28.6 MHz still benefit from controlled-impedance traces for clock and JTAG signals. Use a PLCC extraction tool (not a screwdriver) when replacing the EP1810LC-35 in the field to avoid pin damage.
Compliance Information
The EP1810LC-35 is a 1980s-era Classic EPLD originally manufactured by Altera and now sustained by Rochester Electronics. RoHS/REACH compliance was not tracked when the part was originally released; current Rochester-sold inventory compliance status is not stated in the verified web data and is therefore marked 'unknown'. For modern RoHS-compliant designs, choose a MAX II/MAX V CPLD instead.
