EP1810LC-35 vs EP1810LC-30 Comparison
Detailed side-by-side comparison of EP1810LC-35 by Rochester Electronics and EP1810LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Last Time Buy
Specification Comparison
| Parameter | EP1810LC-35 | EP1810LC-30 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $49.20 | $9.95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, low-power (LC) |
| Package | 68-pin PLCC (J-Lead) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Mounting Type | Surface Mount (socketable) | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| RoHS Status | [DATA_NEEDED] | unknown (legacy ceramic package) |
| Lead-Free | [DATA_NEEDED] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Supply Voltage | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Number of Pins | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |