EP1810LI-45 vs EP1810JC-45 Comparison

Detailed side-by-side comparison of EP1810LI-45 by Rochester Electronics and EP1810JC-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LI-45 EP1810JC-45
Brand Rochester Electronics Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active NRND
Stock Status In Stock In Stock
Unit Price (USD) $64.10 $21.10
Product Type EPLD (Erasable Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Family Altera Classic EP1810 (Classic EPLD Family)
Usable Gates 900 —
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration CMOS, UV-erasable
Supply Voltage 5 V —
Operating Temperature Range -40 C to +85 C (Industrial, 'I' suffix) —
Package 68-pin PLCC / PQCC68 (J-Lead) PLCC-68 (QCCJ, J-Lead, windowed ceramic)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance not stated in verified data]
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) —
Equivalent Gates — 2100 gates
Dedicated Inputs — 12
I/O Pins — 48
Total User I/O — 60
Propagation Delay (tpd) — 45 ns
Maximum Clock Frequency — 33.3 MHz
Maximum Supply Voltage — 5.25 V
Pin Count — 68
Package Code — QCCJ
Temperature Grade — Commercial
Mounting Type — Surface Mount

Datasheets & Resources

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