EP1810LI-45 vs EP1810JI-45 Comparison
Detailed side-by-side comparison of EP1810LI-45 by Rochester Electronics and EP1810JI-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ Active
Specification Comparison
| Parameter | EP1810LI-45 | EP1810JI-45 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $64.10 | $9.75 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic | — |
| Usable Gates | 900 | — |
| Macrocells | 48 | — |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | CMOS EPROM |
| Supply Voltage | 5 V | 5 V (TTL compatible) |
| Operating Temperature Range | -40 C to +85 C (Industrial, 'I' suffix) | — |
| Package | 68-pin PLCC / PQCC68 (J-Lead) | — |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | UV-erase (windowed) / OTP via JEDEC |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 50 ns |
| Configurable I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Operating Temperature | — | -40 °C to +85 °C |