EP1830-20CFN vs EP1810LC-25 Comparison

Detailed side-by-side comparison of EP1830-20CFN by Texas Instruments and EP1810LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Texas Instruments
EP1830-20CFN EP1830-20CFN - 48-Macrocell CMOS EPLD, 22ns, PLCC-68 | TI

EP1830-20CFN - 48-Macrocell CMOS EPLD, 22ns, PLCC-68 | TI

EP1830-20CFN Obsolete

Specification Comparison

Parameter EP1830-20CFN EP1810LC-25
Brand Texas Instruments Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $8.40
Device Type Erasable Programmable Logic Device (EPLD) —
Technology CMOS EPROM CMOS EPLD (erasable programmable logic device)
Macrocell Count 48 —
Propagation Delay (tPD) 22 ns 25 ns
Maximum Supply Voltage 5.25 V —
I/O Pins 48 48
Dedicated Inputs 12 12
Package PLCC-68 (QCCJ, J-lead) 68-pin JLCC (J-leaded ceramic chip carrier)
Terminal Pitch 1.27 mm —
Terminal Form J-Bend —
Package Code QCCJ LC = 68-pin JLCC
Package Shape Square —
Operating Temperature Grade Commercial (0C to 70C) —
Typical Operating Current 20 mA at 1 MHz —
Maximum Counter Frequency 50 MHz (4 x 12-bit counters) —
Speed Grade -20 —
Configuration Memory Non-volatile EPROM (UV-erasable) —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Macrocells — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Mounting Type — Surface Mount
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Lifecycle Status — Obsolete (legacy Altera Classic family)
Operating Temperature — [DATA_NEEDED: temperature grade for LC package]

Datasheets & Resources

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