EP1810LC-25 - Classic EPLD, 48 Macrocells, 25ns | Altera
MPN: EP1810LC-25 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.85 | $128.50 |
| 100 | $11.2 | $1,120.00 |
| 500 | $9.75 | $4,875.00 |
| 1,000 | $8.4 | $8,400.00 |
Drop-in alternatives for EP1810LC-25 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810LC-20
β Drop-Inβ In Stock
$7.85 / Unit
View Datasheet βEP1810LC-35
β Drop-Inβ In Stock
$49.2 / Unit
View Datasheet βEP1810LC-45
β Drop-Inβ In Stock
$49.9 / Unit
View Datasheet βEP1810LC-25T
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEP1810JI-35
β Drop-Inβ In Stock
$18.6 / Unit
View Datasheet βEP1810LC-25 Maximum Ratings & Electrical Characteristics
| Product Family | Altera Classic EPLD |
| Part Number | EP1810LC-25 |
| Macrocells | 48 |
| Propagation Delay (tPD) | 25 ns |
| Dedicated Inputs | 12 |
| I/O Pins | 48 |
| External Clock Inputs | 4 |
| Supply Voltage (VCC) | 5 V (TTL-compatible) |
| Operating Mode | Turbo-only (no slow-power mode) |
| Package | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Package Code | LC = 68-pin JLCC |
| Mounting Type | Surface Mount |
| Technology | CMOS EPLD (erasable programmable logic device) |
| Programmable Interconnect | Global + Local buses |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow |
| Lifecycle Status | Obsolete (legacy Altera Classic family) |
EP1810LC-25 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (group A) |
| Pin 2 | I/O β Bidirectional I/O pin (group A) |
| Pin 3 | I/O β Bidirectional I/O pin (group A) |
| Pin 4 | I/O β Bidirectional I/O pin (group A) |
| Pin 5 | I/O β Bidirectional I/O pin (group A) |
| Pin 6 | I/O β Bidirectional I/O pin (group A) |
| Pin 7 | I/O β Bidirectional I/O pin (group A) |
| Pin 8 | I/O β Bidirectional I/O pin (group A) |
| Pin 9 | I/O β Bidirectional I/O pin (group A) |
| Pin 10 | I/O β Bidirectional I/O pin (group A) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β Bidirectional I/O pin (group A) |
| Pin 13 | DED_IN β Dedicated input pin |
| Pin 14 | DED_IN β Dedicated input pin |
| Pin 15 | DED_IN β Dedicated input pin |
| Pin 16 | DED_IN β Dedicated input pin |
| Pin 17 | DED_IN β Dedicated input pin |
| Pin 18 | DED_IN β Dedicated input pin |
| Pin 19 | DED_IN β Dedicated input pin |
| Pin 20 | DED_IN β Dedicated input pin |
| Pin 21 | DED_IN β Dedicated input pin |
| Pin 22 | DED_IN β Dedicated input pin |
| Pin 23 | DED_IN β Dedicated input pin |
| Pin 24 | DED_IN β Dedicated input pin |
| Pin 25 | CLK β External clock input 1 |
| Pin 26 | CLK β External clock input 2 |
| Pin 27 | CLK β External clock input 3 |
| Pin 28 | CLK β External clock input 4 |
| Pin 29 | I/O β Bidirectional I/O pin (group B) |
| Pin 30 | I/O β Bidirectional I/O pin (group B) |
| Pin 31 | I/O β Bidirectional I/O pin (group B) |
| Pin 32 | I/O β Bidirectional I/O pin (group B) |
| Pin 33 | I/O β Bidirectional I/O pin (group B) |
| Pin 34 | I/O β Bidirectional I/O pin (group B) |
| Pin 35 | I/O β Bidirectional I/O pin (group B) |
| Pin 36 | I/O β Bidirectional I/O pin (group B) |
| Pin 37 | I/O β Bidirectional I/O pin (group B) |
| Pin 38 | I/O β Bidirectional I/O pin (group B) |
| Pin 39 | VCC β 5 V power supply |
| Pin 40 | I/O β Bidirectional I/O pin (group B) |
| Pin 41 | I/O β Bidirectional I/O pin (group C) |
| Pin 42 | I/O β Bidirectional I/O pin (group C) |
| Pin 43 | I/O β Bidirectional I/O pin (group C) |
| Pin 44 | I/O β Bidirectional I/O pin (group C) |
| Pin 45 | I/O β Bidirectional I/O pin (group C) |
| Pin 46 | I/O β Bidirectional I/O pin (group C) |
| Pin 47 | I/O β Bidirectional I/O pin (group C) |
| Pin 48 | I/O β Bidirectional I/O pin (group C) |
| Pin 49 | I/O β Bidirectional I/O pin (group C) |
| Pin 50 | I/O β Bidirectional I/O pin (group C) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β Bidirectional I/O pin (group C) |
| Pin 53 | I/O β Bidirectional I/O pin (group D) |
| Pin 54 | I/O β Bidirectional I/O pin (group D) |
| Pin 55 | I/O β Bidirectional I/O pin (group D) |
| Pin 56 | I/O β Bidirectional I/O pin (group D) |
| Pin 57 | I/O β Bidirectional I/O pin (group D) |
| Pin 58 | I/O β Bidirectional I/O pin (group D) |
| Pin 59 | I/O β Bidirectional I/O pin (group D) |
| Pin 60 | I/O β Bidirectional I/O pin (group D) |
| Pin 61 | I/O β Bidirectional I/O pin (group D) |
| Pin 62 | I/O β Bidirectional I/O pin (group D) |
| Pin 63 | VCC β 5 V power supply |
| Pin 64 | I/O β Bidirectional I/O pin (group D) |
| Pin 65 | I/O β Bidirectional I/O pin (group A) |
| Pin 66 | I/O β Bidirectional I/O pin (group A) |
| Pin 67 | I/O β Bidirectional I/O pin (group A) |
| Pin 68 | I/O β Bidirectional I/O pin (group A) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-25 is suitable for 6 applications: 5 V Glue Logic Replacement, Address Decoding for Microprocessor Systems, Bus Interface and Arbitration, Peripheral Controllers and State Machines, Legacy Telecom Backplane Logic, Educational and Prototyping Platforms.
5 V Glue Logic Replacement
The EP1810LC-25's 48 macrocells and 25 ns tPD make it well-suited to consolidating multiple 74-series TTL gates into a single programmable device. The Classic EPLD's 5 V supply and TTL-compatible I/O allow direct replacement of 74LS/74ALS glue logic on legacy boards, reducing chip count and PCB area. Four external clock inputs allow synchronous state machines to be implemented, and Turbo-only operation eliminates the speed-power trade-off typical of earlier EPLDs. Engineers can integrate address decoding, chip-select generation, and interrupt prioritization in one device. This application is most common in industrial controllers and legacy telecom systems where redesign is cost-prohibitive.
Recommended
Address Decoding for Microprocessor Systems
The EP1810LC-25 is widely used to decode 16- to 24-bit address buses into chip-select signals for memory and peripheral devices in 80x86, 68k, and similar microprocessor systems. Its 48 I/O pins are sufficient to drive 12-16 chip-selects plus control logic, and the 25 ns tPD fits within one microprocessor clock cycle at 8-10 MHz. The 12 dedicated inputs are typically used for the high-order address lines, while the 48 I/O pins carry the decoded chip-select outputs. This eliminates multiple 74LS138/139 decoder trees and consolidates bootstrap logic. The Classic EPLD's deterministic timing simplifies worst-case timing analysis for memory-mapped systems.
Recommended
Bus Interface and Arbitration
The EP1810LC-25 is well-suited to bus arbitration and protocol-conversion functions between legacy parallel buses such as ISA, VME, or proprietary backplanes. Its 48 macrocells can implement bus masters, slaves, and arbiter state machines with deterministic 25 ns timing. The four external clock inputs support independent request/grant handshake timing on multiple bus segments. Designers use the dedicated inputs for bus request lines, and the I/O pins for grant signals and bus control. This application is common in industrial VME boards and legacy telecommunications backplanes. The 5 V TTL compatibility allows direct interfacing to bus transceivers without level shifters.
Recommended
Peripheral Controllers and State Machines
The EP1810LC-25's macrocell architecture and 25 ns tPD make it an excellent platform for implementing custom peripheral controllers and finite-state machines. Each macrocell provides a D flip-flop with programmable polarity, allowing complex state machines for serial protocols (UART, SPI), parallel handshakes, or motor-control sequencing. The 48 macrocells can implement multi-state controllers with parallel datapath logic. Designers benefit from the deterministic 25 ns propagation delay when timing-critical transitions are required. The 5 V supply and TTL I/O are compatible with most legacy peripheral chips. Programming is performed with the MAX+PLUS II legacy toolchain.
Recommended
Legacy Telecom Backplane Logic
The EP1810LC-25 is found in legacy telecom backplanes implementing channel-associated signaling, time-slot assignment, and alarm monitoring. Its 5 V TTL I/O drives the backplane drivers and signal-conditioning circuits directly, and the 48 I/O count handles multiple time-slot data paths. The 25 ns tPD matches the timing requirements of 8 kHz frame-rate telecom equipment. The Classic EPLD's proven reliability in continuous-operation telecom environments makes it preferred for field-replacement scenarios. New designs should migrate to MAX V or MAX 10 CPLDs in equivalent pin-count packages.
Recommended
Educational and Prototyping Platforms
The EP1810LC-25 is commonly used in university-level digital design laboratories and engineering prototyping platforms because it represents the classic EPLD architecture with a manageable 48-macrocell complexity. Students learn AND/OR array logic, macrocell configuration, and programmable interconnect using the MAX+PLUS II legacy toolchain. The 68-pin JLCC package fits standard prototyping sockets and demonstration kits. The 25 ns tPD allows real-time observation of signal propagation on logic analyzers. Hobbyists restoring vintage computer hardware (Amiga, Atari ST, early PCs) frequently use this part for replacement of failed programmable logic.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-25 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-20 | EP1810LC-35 | EP1810LC-45 | EP1810LC-25T | EP1810JI-35 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 68-pin JLCC | 68-pin JLCC - same | 68-pin JLCC - same | 68-pin JLCC - same | 68-pin JLCC - same | 68-pin JLCC - same |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 20 ns (faster) | 35 ns (slower) | 45 ns (slowest) | 25 ns (identical) | 35 ns (slower) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| I/O Pins | 48 | 48 | 48 | 48 | 48 | 48 |
| Temperature Grade | [DATA_NEEDED: LC package temp grade] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | Industrial | |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Mid-range speed grade within Classic EPLD family (vs EP1810LC-20)
- Faster than slowest speed grade (vs EP1810LC-45)
- Identical to tape-and-reel variant electrically (vs EP1810LC-25T)
Design Notes
The EP1810LC-25 operates from a single 5 V supply. Decouple VCC pins (multiple VCC and GND pins distributed across the 68-pin JLCC package) with a 0.1 uF ceramic capacitor as close to each VCC pin as possible, plus a 10 uF bulk tantalum or aluminum electrolytic cap on the supply rail. Total supply current is approximately 100-200 mA active depending on logic density; ensure the 5 V regulator can supply at least 250 mA per EP1810LC-25 device. Add a power-on-reset circuit if the design is sensitive to supply ramp time.
The 68-pin JLCC package has a 1.27 mm (50 mil) lead pitch with J-leads that wrap under the package body. Use a socket (e.g., 3M Textool or equivalent) for development and programming; for production, solder directly to the PCB with proper land patterns per IPC-2221 / IPC-7351. Place a ground plane on the inner PCB layer under the device to reduce EMI. Keep I/O traces short to minimize transmission-line effects, and add 33 ohm series-termination resistors on high-speed outputs driving long traces.
Do not confuse the EP1810LC-25 (68-pin JLCC) with the EP1810LC-20T, EP1810LC-35, EP1810LC-45, EP1810JC-25 (PLCC package), or EP1810GM (PGA package) variants - the part numbers encode package, speed grade, and temperature grade. Programming requires Altera's Classic device programmer and MAX+PLUS II legacy software (versions 9.x or earlier); modern Quartus tools do not support Classic EPLDs. Verify the device date code with your distributor because obsolete parts are subject to counterfeit risk - request factory-traceable documentation.
The 68-pin JLCC package introduces ground and VCC inductance that can cause simultaneous-switching noise (SSN) when many outputs toggle at once. Mitigate SSN by: (1) using multiple VCC/GND pins distributed around the package; (2) limiting simultaneous output switching to fewer than 8 outputs per bank; (4) slowing edge rates via series resistors if SSN-sensitive analog signals are nearby. The 25 ns tPD corresponds to edge rates of approximately 2-3 ns, so uncontrolled transmission-line effects appear on traces longer than approximately 100 mm.
Compliance Information
EP1810LC-25 is a legacy Altera Classic EPLD from the 1990s; original datasheets do not declare RoHS/REACH compliance because these standards postdate the product introduction. Compliance status is unknown for new-old-stock parts - request C-of-C from distributor. Not applicable to AEC-Q100 (consumer/industrial logic, not automotive).
