EP1S80F1020C6 vs EP1S80F1020I7NGA Comparison
Detailed side-by-side comparison of EP1S80F1020C6 by Intel and EP1S80F1020I7NGA by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1S80F1020C6 | EP1S80F1020I7NGA |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,180.00 | $188.00 |
| Series | Stratix | — |
| Logic Elements | 79,040 | 79,040 |
| Total RAM Bits | 7,427,520 | — |
| Number of Logic Blocks / LABs | 9,191 | — |
| Number of I/O Pins (max) | 773 user I/O | — |
| Number of Pins / Balls | 1020 | — |
| Package Type | FC-FBGA (flip-chip fine-pitch BGA), 33 x 33 mm, 1.0 mm pitch | — |
| Process Technology | 130 nm CMOS | — |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | — |
| Speed Grade | C6 | — |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| Family Description | FPGA - Field Programmable Gate Array | — |
| Embedded Memory | TriMatrix (three block sizes, true/simple dual-port) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel configuration device | — |
| Design Tool | Quartus II (legacy, Stratix family) | — |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant |
| Moisture Sensitivity Level (MSL) | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020) |
| Family | — | Stratix (EP1S) |
| Total Memory Bits | — | 7,427,520 bits |
| DSP Blocks | — | 22 |
| Embedded Transceivers | — | 12 channels (600 Mbps to 3.1875 Gbps) |
| Maximum User I/O | — | 773 |
| Package | — | 1020-ball FineLine BGA (33 × 33 mm, 1.00 mm pitch) |
| Process Node | — | 0.13 µm CMOS |
| Operating Temperature | — | -40 °C to +100 °C (Industrial) |
| Supply Voltage (Core) | — | 1.5 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, SSTL, LVDS, LVPECL, PCI, PCI-X, HSTL, LVDS, HyperTransport |
| Maximum Clock Frequency | — | Up to 420 MHz (device-dependent) |
| PLL Count | — | 12 (enhanced PLLs and fast PLLs) |
| Configuration Method | — | JTAG, EPC16/EPC8 serial or parallel configuration device, passive/active serial |
| Lead-Free | — | Yes |