EP20K100EBC356-3N vs EP20K100CB356C7 Comparison
Detailed side-by-side comparison of EP20K100EBC356-3N by Altera and EP20K100CB356C7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K100CB356C7 - APEX20K FPGA 100K Gates 252 I/O 356-BGA | Intel
EP20K100CB356C7 ⚠ Last Time BuySpecification Comparison
| Parameter | EP20K100EBC356-3N | EP20K100CB356C7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Series | APEX-20KE | APEX20K |
| Family | APEX 20K | — |
| Logic Elements / Cells | 4160 | — |
| System Gates | 100,000 | — |
| Embedded Memory (bits) | 53,248 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum User I/Os | 246 | — |
| Number of Pins | 356 | — |
| Package | 356-LBGA (Ball Grid Array) | 356-LBGA |
| Package Dimensions | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 0.22 µm CMOS | 0.18 μm CMOS |
| Core Supply Voltage | 1.8 V | — |
| Propagation Delay | 1.6 ns (speed grade -3N) | — |
| Maximum Internal Frequency | 250 MHz | — |
| Operating Temperature | 0 °C to +85 °C | Commercial grade |
| Mounting Type | Surface Mount | — |
| Programmable Interface | JTAG (IEEE 1149.1) | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | 1.8V, 2.5V, 3.3V, 5V (MultiVolt) |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | — | Intel (formerly Altera) |
| Typical Gates | — | 100,000 |
| Maximum Logic Elements | — | 53,248 |
| User I/O Pins | — | 252 |
| Embedded Memory (Bits) | — | 53,248 |
| Number of PLLs | — | 4 |
| Core Voltage | — | 2.5 V |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Speed Grade | — | C7 |