EP20K100EBC356-3N vs EP20K200BC356-2 Comparison
Detailed side-by-side comparison of EP20K100EBC356-3N by Altera and EP20K200BC356-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K100EBC356-3N | EP20K200BC356-2 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | APEX-20KE | APEX-20K |
| Family | APEX 20K | — |
| Logic Elements / Cells | 4160 | — |
| System Gates | 100,000 | — |
| Embedded Memory (bits) | 53,248 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum User I/Os | 246 | — |
| Number of Pins | 356 | — |
| Package | 356-LBGA (Ball Grid Array) | 356-LBGA (35 mm × 35 mm) |
| Package Dimensions | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm |
| Core Supply Voltage | 1.8 V | 2.5 V |
| Propagation Delay | 1.6 ns (speed grade -3N) | 2.5 ns |
| Maximum Internal Frequency | 250 MHz | — |
| Operating Temperature | 0 °C to +85 °C | 0 °C to +85 °C (commercial) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Programmable Interface | JTAG (IEEE 1149.1) | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | — |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | APEX-20K (MultiCore PLD) |
| Logic Elements | — | 8,320 |
| Typical Gate Count | — | 200,000 gates |
| Embedded Memory | — | 106,496 bits |
| User I/Os | — | 277 |
| Logic Family | — | CMOS |
| Speed Grade | — | -2 |
| Maximum Frequency | — | 200 MHz |