EP20K200BC356-1 vs EP20K200EBC356-1 Comparison

Detailed side-by-side comparison of EP20K200BC356-1 by Altera and EP20K200EBC356-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K200BC356-1 EP20K200BC356-1 - APEX-20K 200K-Gate FPGA | Altera

EP20K200BC356-1 - APEX-20K 200K-Gate FPGA | Altera

EP20K200BC356-1 Obsolete

Specification Comparison

Parameter EP20K200BC356-1 EP20K200EBC356-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Product Function APEX-20K Field Programmable Gate Array (FPGA) —
Logic Family CMOS —
Equivalent System Gates 200K gates —
Logic Elements / Cells 8320 8,320
Total RAM Bits 106496 bits —
Maximum Clock Frequency 250 MHz —
Core Supply Voltage 2.5 V —
User I/O Count 277 —
Number of Pins 356 —
Package / Case 356-LBGA —
Package Code LBGA —
Package Shape Square —
Mounting Type Surface Mount Surface Mount (BGA)
Process Technology 0.22 um 0.22 µm CMOS
Propagation Delay (tPD) 2.5 ns (from -1N variant listing) —
Operating Temperature Range 0 to 85 C (commercial, per -1N variant listing) —
RoHS Status [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] [DATA_NEEDED: RoHS status not stated in verified sources]
Lead-Free Finish [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] —
Family — APEX 20K (APEX 20KE)
System Gates — 200,000
Maximum User I/Os — 277
Core Voltage — 1.8 V (1.71 V to 1.89 V)
Propagation Delay — 2.5 ns
Internal Performance — Up to 367 MHz
Package — 356-ball LBGA (35 x 35 mm)
Operating Temperature — 0 °C to 85 °C (Commercial)
Architecture — MultiCore (LUT + product-term + embedded memory)
On-chip Memory — Embedded System Blocks (ESB / SRAM)
Configuration Method — JTAG (ByteBlaster / MasterBlaster), passive serial
Development Software — Altera Quartus II
Lifecycle Status — Obsolete / EOL

Datasheets & Resources

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