EP20K200FC484-1 vs EP20K200EFC484-1 Comparison
Detailed side-by-side comparison of EP20K200FC484-1 by Altera and EP20K200EFC484-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 ⚠ Last Time BuySpecification Comparison
| Parameter | EP20K200FC484-1 | EP20K200EFC484-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Family | APEX 20K | APEX 20KE |
| Logic Elements / Cells | 8320 | 8320 |
| System Gates | 200 K | 200000 |
| Embedded Memory (RAM bits) | 106,496 bits | — |
| Number of I/Os | 382 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Supply Voltage | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Maximum Operating Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Operating Temperature | 0 °C to 85 °C (Commercial) | -40 °C to +85 °C (industrial, inferred from grade code) |
| Package | 484-ball FBGA (FineLine BGA) | 484-BGA (FineLine BGA) |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Interface | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG, passive serial, passive parallel |
| Speed Grade | -1 (fastest bin) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Embedded Memory (Bits) | — | 106496 |
| Maximum User I/O | — | 376 |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| Package Ball Count | — | 484 |
| I/O Standard Support | — | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL |
| MSL Level | — | [DATA_NEEDED: MSL moisture sensitivity level] |