EP20K200FC484-1 vs EP20K200EFC484-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200FC484-1 sa pamamagitan ng Altera at EP20K200EFC484-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K200FC484-1 | EP20K200EFC484-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX 20K | APEX 20KE |
| Logic Elements / Cells | 8320 | 8320 |
| System Gates | 200 K | 200000 |
| Embedded Memory (RAM bits) | 106,496 bits | — |
| Number of I/Os | 382 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Supply Voltage | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Maximum Operating Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Temperature na Operasyon | 0 °C to 85 °C (Commercial) | -40 °C to +85 °C (industrial, inferred from grade code) |
| Packhaging | 484-ball FBGA (FineLine BGA) | 484-BGA (FineLine BGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Interface | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG, passive serial, passive parallel |
| Speed Grade | -1 (fastest bin) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Embedded Memory (Bits) | — | 106496 |
| Maximum User I/O | — | 376 |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| Package Ball Count | — | 484 |
| I/O Standard Support | — | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL |
| Level ng MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |