EP20K200FC484-1 vs EP20K200FC484-1N Comparison

Detailed side-by-side comparison of EP20K200FC484-1 by Altera and EP20K200FC484-1N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K200FC484-1 EP20K200FC484-1 - APEX 20K 200K Gates FPGA | Altera

EP20K200FC484-1 - APEX 20K 200K Gates FPGA | Altera

EP20K200FC484-1 Obsolete

Specification Comparison

Parameter EP20K200FC484-1 EP20K200FC484-1N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family APEX 20K APEX 20K
Logic Elements / Cells 8320 8,320
System Gates 200 K 200,000 (approx.)
Embedded Memory (RAM bits) 106,496 bits —
Number of I/Os 382 —
Number of LABs/CLBs [DATA_NEEDED: LAB count] —
Core Supply Voltage 2.5 V —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Maximum Operating Frequency 250 MHz —
Propagation Delay 2.5 ns 2.5 ns
Operating Temperature 0 °C to 85 °C (Commercial) 0 °C to +85 °C
Package 484-ball FBGA (FineLine BGA) 484-FBGA (23 x 23 mm)
Mounting Type Surface Mount Surface Mount
Architecture MultiCore (LUT + Embedded System Blocks) MultiCore (LUT + product-term + embedded memory)
Programming Interface IEEE 1149.1 JTAG —
Speed Grade -1 (fastest bin) —
RoHS Status [DATA_NEEDED: RoHS status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Series — APEX-20K®
Maximum User I/O — 382
Number of Macros — 832
Supply Voltage (Core) — 2.5 V (2.375 V – 2.625 V)
Maximum Internal Frequency — 250 MHz
Package Code — BGA / FBGA
Number of Pins/balls — 484
Lead-Free / RoHS — Compliant (per distributor listings)
Configuration Method — SRAM-based, JTAG/ByteBlaster

Datasheets & Resources

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