EP20K300EQC240-2XN vs EP20K300EQC240-3 Comparison

Detailed side-by-side comparison of EP20K300EQC240-2XN by Intel and EP20K300EQC240-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K300EQC240-2XN EP20K300EQC240-3
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Series APEX-20KE —
Number of Logic Elements / Cells 11520 —
Number of LABs/CLBs 1152 —
Number of Macrocells [DATA_NEEDED: macrocells] —
Maximum User I/O Pins 152 —
Total RAM Bits 147456 —
System Gates (datasheet) 728000 —
Family Gates (ordering code) 300000 —
Maximum Internal Clock 350 MHz —
Core Supply Voltage (VCCINT) 1.8 V —
Supply Voltage Range 1.71 V to 1.89 V —
Speed Grade -2 -3
Operating Temperature Range 0 to +85 °C (TJ) —
Process Technology 0.22 um CMOS 0.22 um CMOS
Package / Case 240-PQFP / 240-BQFP (32x32 mm) —
Mounting Type Surface Mount Surface Mount
Lifecycle Status Obsolete (EOL) —
Lead-Free Yes (N suffix) —
RoHS unknown —
MSL Level [DATA_NEEDED: MSL level] —
ECCN [DATA_NEEDED: ECCN] —
Family — APEX-20KE
Typical Gates — 300,000
Logic Elements / Cells — 11,520
Embedded Memory (bits) — 147,456
Maximum User I/O — 152
Number of PLLs — 4
Core Voltage (VCCINT) — 1.8 V
I/O Voltage Tolerance — 2.5V / 3.3V / 5.0V compatible
Package — 240-pin PQFP / BFQFP (240-BFQFP)
Pin Pitch — 1.0 mm
Terminal Form — Gull Wing
Operating Temperature — 0C to +85C (commercial)
Programmable Logic Type — Loadable PLD
Architecture — MultiCore (LUT + Embedded System Blocks)
Configuration Interface — JTAG (IEEE 1149.1), passive serial
RoHS Status — [DATA_NEEDED: confirm for this date code]

Datasheets & Resources

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