EP20K30EFC144-1N vs EP20K60EFC144-2 Comparison

Detailed side-by-side comparison of EP20K30EFC144-1N by Intel and EP20K60EFC144-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP20K30EFC144-1N EP20K30EFC144-1N - APEX-20KE 30K Gates FPGA | Intel

EP20K30EFC144-1N - APEX-20KE 30K Gates FPGA | Intel

EP20K30EFC144-1N Obsolete

Specification Comparison

Parameter EP20K30EFC144-1N EP20K60EFC144-2
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Series APEX-20KE APEX-20K
Device Family APEX-20K MultiCore (LUT + Product-Term + ESB) —
Gates 30,000 —
Logic Elements 1,200 2,560
Embedded SRAM Bits 24,576 —
User I/Os 93 (per Mouser/Kynix listing); 408 (per alternate datasheet listing - see note) —
Package Type 144-pin FineLine BGA (FBGA) —
Internal Frequency (max) 160 MHz 160 MHz
Propagation Delay 1.68 ns 1.72 ns
Logic Family CMOS —
Core Technology 0.22 µm CMOS, SRAM-based configuration —
Supply Voltage (Core) 1.71 V to 1.89 V (1.8 V nominal) —
Operating Temperature 0 °C to 85 °C (commercial, N suffix) 0 °C to +85 °C (commercial)
Configuration Interface IEEE 1149.1 JTAG + serial configuration (external EPCx required) —
Mounting Type Surface Mount Surface Mount
RoHS Status Unknown - not stated in verified sources [DATA_NEEDED: RoHS status]
Family — APEX-20KE (Enhanced, 1.8 V core)
Typical Gates — 60,000
Total RAM Bits — 32,768
User I/O — 92 to 93
Core Supply Voltage — 1.71 V to 1.89 V
Process Technology — 0.18 µm CMOS
Package — 144-LQFP (also referenced as 144-FBGA 13x13 in some sources)
JTAG Support — IEEE 1149.1 boundary scan
I/O Standards — LVTTL, LVCMOS, PCI, GTL+
Configuration Method — Serial/Parallel passive, JTAG, EPC companion

Datasheets & Resources

Browse All Products Create BOM Request Quote