EP20K400CF672I9 vs EP20K400CF672I8 Comparison
Detailed side-by-side comparison of EP20K400CF672I9 by Intel and EP20K400CF672I8 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672I9 | EP20K400CF672I8 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $120.00 | $0.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 16,640 cells | β |
| System Gates | 400,000 | 400,000 |
| Maximum Operating Frequency | 250 MHz | β |
| Embedded RAM | 212,992 bits | β |
| Embedded System Blocks (ESBs) | 104 | β |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS |
| Core Voltage | 1.8 V | β |
| I/O Voltage | 1.8 V / 3.3 V (MultiVolt) | β |
| Package | 672-ball FC-FBGA (FineLine BGA) | β |
| Package Pitch | 1.0 mm | β |
| Operating Temperature | -40Β°C to +85Β°C (Industrial) | β |
| Speed Grade | I9 (Industrial) | I8 |
| Moisture Sensitivity Level (MSL) | 3 | β |
| Terminal Finish | e0 (Tin-Lead, per JESD-609) | β |
| RoHS Status | Non-compliant (e0 terminal finish indicates SnPb) | [DATA_NEEDED: RoHS compliance] |
| Series | β | EP20K400 |
| Manufacturer | β | Intel (formerly Altera) |
| Device Type | β | FPGA - Field Programmable Gate Array |
| Logic Elements / Cells | β | 16,640 |
| Embedded Memory (RAM bits) | β | 212,992 |
| Number of Logic Macros | β | 1664 |
| User I/O Pins | β | 488 |
| Supply Voltage - Core | β | 1.8 V |
| I/O Voltage (MultiVolt) | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Maximum Internal Frequency | β | 301.21 MHz |
| Package Type | β | 672-pin FC-FBGA (FineLine BGA) |
| Operating Temperature (Industrial) | β | -40 Β°C to +100 Β°C |
| Mounting Type | β | Surface Mount (BGA) |
| Configuration Method | β | Passive Serial / Active Serial / JTAG (IEEE 1149.1) |
| PLLs | β | 4 |
| MSL Level | β | [DATA_NEEDED: MSL moisture sensitivity level] |