EP20K400FI672-2V vs EP20K400FI672-3V Comparison

Detailed side-by-side comparison of EP20K400FI672-2V by Intel and EP20K400FI672-3V by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400FI672-2V EP20K400FI672-3V
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family APEX 20K APEX 20K (EP20K400)
Device EP20K400 —
Logic Elements / Cells 16640 —
Total System Gates 400000 —
Embedded Memory Bits 212992 —
Number of I/O 502 —
Package 672-BBGA, FCBGA 672-ball FineLine BGA (BBGA), 1.0 mm pitch
Pin / Ball Count 672 —
Supply Voltage 2.5 V —
Process Technology 0.22 µm CMOS 0.18 µm CMOS, 4 metal layers
Propagation Delay 2.5 ns —
Internal Operating Frequency 200 MHz —
Operating Temperature 0 °C to +85 °C -40 °C to +85 °C (industrial)
Logic Family CMOS —
Mounting Type Surface Mount (BGA) Surface Mount
Configuration Mode Serial / Parallel / JTAG —
RoHS Status [DATA_NEEDED: rohs] [DATA_NEEDED: RoHS status]
MSL Level [DATA_NEEDED: msl] [DATA_NEEDED: MSL rating]
Logic Elements — 16,640
Maximum Gates — 400,000
Typical Gates — [DATA_NEEDED: typical gates value]
Embedded Memory (bits) — 212,992
Maximum User I/O — 502
Dedicated Inputs — 6
Total User I/O + Dedicated Inputs — 496 + 6 (variant dependent)
Maximum Clock Frequency — 714.2 MHz
Speed Grade — -3 (faster)
Core Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
Programmable via JTAG — Yes (IEEE 1149.1)
Supported I/O Standards — LVCMOS, LVTTL, SSTL, GTL+, HSTL
Configuration Modes — JTAG, passive serial, passive parallel

Datasheets & Resources

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