EP20K400FI672-2V vs EP20K400FI672-3V 对比

详细并排对比 EP20K400FI672-2V 出自 Intel 和 EP20K400FI672-3V 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FI672-2V EP20K400FI672-3V
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $285.00
Family APEX 20K APEX 20K (EP20K400)
Device EP20K400 —
Logic Elements / Cells 16640 —
Total System Gates 400000 —
Embedded Memory Bits 212992 —
Number of I/O 502 —
封装 672-BBGA, FCBGA 672-ball FineLine BGA (BBGA), 1.0 mm pitch
Pin / Ball Count 672 —
电源电压 2.5 V —
Process Technology 0.22 µm CMOS 0.18 µm CMOS, 4 metal layers
Propagation Delay 2.5 ns —
Internal Operating Frequency 200 MHz —
工作温度 0 °C to +85 °C -40 °C to +85 °C (industrial)
Logic Family CMOS —
安装类型 Surface Mount (BGA) Surface Mount
Configuration Mode Serial / Parallel / JTAG —
RoHS 状态 [DATA_NEEDED: rohs] [DATA_NEEDED: RoHS status]
MSL 等级 [DATA_NEEDED: msl] [DATA_NEEDED: MSL rating]
Logic Elements — 16,640
Maximum Gates — 400,000
Typical Gates — [DATA_NEEDED: typical gates value]
Embedded Memory (bits) — 212,992
Maximum User I/O — 502
Dedicated Inputs — 6
Total User I/O + Dedicated Inputs — 496 + 6 (variant dependent)
最大时钟频率 — 714.2 MHz
Speed Grade — -3 (faster)
Core Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
Programmable via JTAG — Yes (IEEE 1149.1)
Supported I/O Standards — LVCMOS, LVTTL, SSTL, GTL+, HSTL
Configuration Modes — JTAG, passive serial, passive parallel

数据手册与资源

浏览全部产品 创建 BOM 获取报价