EP20K400FI672-3 vs EP20K400FC672-3 Comparison
Detailed side-by-side comparison of EP20K400FI672-3 by Altera and EP20K400FC672-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400FI672-3 | EP20K400FC672-3 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Series | EP20K400 | — |
| Logic Elements | 16640 | — |
| Total Gates | up to 400000 | — |
| Embedded RAM | 212992 bits | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Propagation Delay | 3.6 ns | 2.5 ns |
| Maximum Clock Frequency | 833 MHz | — |
| Supply Voltage (Nominal) | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | 0.22 µm CMOS |
| Package Type | PBGA (Plastic BGA) | — |
| Package Code | S-PBGA-B672 | BGA |
| Terminal Count | 672 | — |
| Terminal Pitch | 1.000 mm | — |
| Package Shape | Square BGA | — |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Interface | JTAG (IEEE 1149.1) | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 °C to 85 °C |
| MSL Level | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| Device Logic Elements | — | 16,640 cells |
| Typical Gate Count | — | 400,000 system gates |
| Maximum User I/Os | — | 502 |
| Internal Performance | — | 167 MHz |
| Core Supply Voltage | — | 2.5 V |
| Logic Family | — | CMOS, SRAM-based |
| Package | — | 672-pin FC-FBGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Speed Grade | — | -3 (commercial fastest) |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| Lifecycle Status | — | Obsolete / Legacy |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |