EP20K400GC655-1 vs EP20K400GC655-1V Comparison
Detailed side-by-side comparison of EP20K400GC655-1 by Intel and EP20K400GC655-1V by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-1 | EP20K400GC655-1V |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KE |
| Series | EP20K400 | — |
| Logic Elements | 16,640 | 16,640 |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 502 | 496 |
| Dedicated Inputs | 6 | 6 |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | 250 MHz (-1V speed grade) |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Package | 655-pin CPGA (Ceramic Pin Grid Array) | CBGA-655 (Ceramic Ball Grid Array) |
| Pin Count | 655 | — |
| Mounting Type | Through-Hole | — |
| Operating Temperature | 0 °C to +85 °C (commercial) | — |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| RoHS Status | Non-compliant (contains lead in ceramic package) | — |
| Typical Gate Count | — | 400,000 gates |
| Embedded Memory | — | 212,992 bits |
| Total Terminals | — | 655 |
| Supply Voltage (Core) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| LVDS Support | — | Yes |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 °C |
| Qualification | — | Not Qualified |
| Programming Interface | — | IEEE 1532 / JTAG |