EP20K400GC655-1 vs EP20K400GC655-2N Comparison
Detailed side-by-side comparison of EP20K400GC655-1 by Intel and EP20K400GC655-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-1 | EP20K400GC655-2N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $135.00 | $127.50 |
| Family | APEX 20K | APEX 20KC |
| Series | EP20K400 | β |
| Logic Elements | 16,640 | β |
| Maximum Gates | 1,052,000 | β |
| Typical Gates | 400,000 | β |
| Embedded System Blocks (ESBs) | 4 | β |
| Total RAM Bits | 212,992 | 212992 |
| Maximum User I/O | 502 | β |
| Dedicated Inputs | 6 | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m CMOS |
| Core Supply Voltage | 2.5 V | β |
| I/O Supply Voltage | 3.3 V | β |
| Maximum Internal Frequency | 250 MHz | β |
| Propagation Delay | 2.5 ns | β |
| Package | 655-pin CPGA (Ceramic Pin Grid Array) | β |
| Pin Count | 655 | β |
| Mounting Type | Through-Hole | Through-Hole (CPGA, socket-compatible) |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | Industrial (per Altera part-number -N suffix) |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | β |
| Boundary Scan | IEEE 1149.1 (JTAG) | β |
| RoHS Status | Non-compliant (contains lead in ceramic package) | [DATA_NEEDED: RoHS status] |
| Number of Logic Elements | β | 16640 |
| Number of Logic Cells | β | 16640 |
| Total System Gates | β | 400000 |
| Number of I/O | β | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | β | [DATA_NEEDED: LAB count] |
| Core Voltage (VCCINT) | β | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | β | 2.5 V (LVDS-capable) |
| Maximum Operating Frequency | β | 200 MHz |
| Propagation Delay (Tpd) | β | 3.1 ns |
| Package / Case | β | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | β | 655-CPGA, 62.48 x 62.48 mm |
| LVDS Support | β | Yes |
| Architecture | β | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | β | JTAG / Passive Serial |
| MSL Level | β | [DATA_NEEDED: MSL level] |