EP20K400GC655-1 vs EP20K400GC655-2N Comparação
Comparação detalhada lado a lado de EP20K400GC655-1 por Intel e EP20K400GC655-2N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteComparação de especificações
| Parâmetro | EP20K400GC655-1 | EP20K400GC655-2N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $135,00 | $127,50 |
| Family | APEX 20K | APEX 20KC |
| Series | EP20K400 | — |
| Logic Elements | 16,640 | — |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | 212992 |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Encapsulamento | 655-pin CPGA (Ceramic Pin Grid Array) | — |
| Contagem de pinos | 655 | — |
| Tipo de montagem | Through-Hole | Through-Hole (CPGA, socket-compatible) |
| Temperatura de operação | 0 °C to +85 °C (commercial) | Industrial (per Altera part-number -N suffix) |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| Status RoHS | Non-compliant (contains lead in ceramic package) | [DATA_NEEDED: RoHS status] |
| Number of Logic Elements | — | 16640 |
| Number of Logic Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | — | 2.5 V (LVDS-capable) |
| Maximum Operating Frequency | — | 200 MHz |
| Propagation Delay (Tpd) | — | 3.1 ns |
| Encapsulamento / Caixa | — | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | — | 655-CPGA, 62.48 x 62.48 mm |
| LVDS Support | — | Yes |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | — | JTAG / Passive Serial |
| Nível MSL | — | [DATA_NEEDED: MSL level] |