EP20K400GC655-1 vs EP20K400GC655-2X Comparison
Detailed side-by-side comparison of EP20K400GC655-1 by Intel and EP20K400GC655-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-1 | EP20K400GC655-2X |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $135.00 | $175.00 |
| Family | APEX 20K | APEX 20K |
| Series | EP20K400 | APEX-20KCยฎ |
| Logic Elements | 16,640 | โ |
| Maximum Gates | 1,052,000 | โ |
| Typical Gates | 400,000 | โ |
| Embedded System Blocks (ESBs) | 4 | โ |
| Total RAM Bits | 212,992 | 212992 |
| Maximum User I/O | 502 | โ |
| Dedicated Inputs | 6 | โ |
| Process Technology | 0.22 ยตm CMOS | 0.22 ยตm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 3.3 V | โ |
| Maximum Internal Frequency | 250 MHz | โ |
| Propagation Delay | 2.5 ns | โ |
| Package | 655-pin CPGA (Ceramic Pin Grid Array) | โ |
| Pin Count | 655 | โ |
| Mounting Type | Through-Hole | Through-hole (CPGA) |
| Operating Temperature | 0 ยฐC to +85 ยฐC (commercial) | [DATA_NEEDED: temperature grade] |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | โ |
| Boundary Scan | IEEE 1149.1 (JTAG) | โ |
| RoHS Status | Non-compliant (contains lead in ceramic package) | unknown |
| Logic Elements / Cells | โ | 16640 |
| System Gates | โ | 400000 |
| Number of I/O | โ | 496 |
| Number of Dedicated Inputs | โ | 6 |
| Number of LABs/CLBs | โ | [DATA_NEEDED: number of Logic Array Blocks] |
| Number of EABs | โ | [DATA_NEEDED: number of Embedded Array Blocks] |
| Maximum Operating Frequency | โ | 200 MHz |
| I/O Supply Voltage (MultiVolt) | โ | 2.5 V / 3.3 V / 5 V |
| Package Type | โ | 655-BCPGA (SPGA655) |
| Package Body Material | โ | CERAMIC, metal-sealed cofired grid array |
| Package Dimensions | โ | 47 x 47 mm |
| Peak Reflow Temperature | โ | 220 ยฐC |
| Programmability | โ | In-system, JTAG (IEEE 1149.1) |