EP20K400GC655-1V vs EP20K400GC655-2N Comparison

Detailed side-by-side comparison of EP20K400GC655-1V by Altera and EP20K400GC655-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400GC655-1V EP20K400GC655-2N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family APEX 20KE APEX 20KC
Logic Elements 16,640 —
Typical Gate Count 400,000 gates —
Embedded Memory 212,992 bits —
Maximum User I/O 496 —
Dedicated Inputs 6 —
Package CBGA-655 (Ceramic Ball Grid Array) —
Total Terminals 655 —
Supply Voltage (Core) 2.375 V to 2.625 V (nominal 2.5 V) —
Propagation Delay 2.5 ns —
Maximum Internal Frequency 250 MHz (-1V speed grade) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
LVDS Support Yes Yes
Moisture Sensitivity Level MSL 1 —
Peak Reflow Temperature 220 °C —
Qualification Not Qualified —
Programming Interface IEEE 1532 / JTAG —
Number of Logic Elements — 16640
Number of Logic Cells — 16640
Total System Gates — 400000
Total RAM Bits — 212992
Number of I/O — [DATA_NEEDED: I/O count]
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Core Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Voltage (VCCIO) — 2.5 V (LVDS-capable)
Maximum Operating Frequency — 200 MHz
Propagation Delay (Tpd) — 3.1 ns
Package / Case — 655-BCPGA (Ceramic Pin Grid Array)
Supplier Device Package — 655-CPGA, 62.48 x 62.48 mm
Operating Temperature — Industrial (per Altera part-number -N suffix)
Mounting Type — Through-Hole (CPGA, socket-compatible)
Architecture — MultiCore (LUT + product-term + embedded memory)
Configuration Method — JTAG / Passive Serial
RoHS Status — [DATA_NEEDED: RoHS status]
MSL Level — [DATA_NEEDED: MSL level]

Datasheets & Resources

Browse All Products Create BOM Request Quote