EP20K400GC655-1V vs EP20K400GC655-2N Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-1V par Altera et EP20K400GC655-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GC655-1V | EP20K400GC655-2N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $555,00 | $127,50 |
| Family | APEX 20KE | APEX 20KC |
| Logic Elements | 16,640 | — |
| Typical Gate Count | 400,000 gates | — |
| Embedded Memory | 212,992 bits | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | — |
| Boîtier | CBGA-655 (Ceramic Ball Grid Array) | — |
| Total Terminals | 655 | — |
| Supply Voltage (Core) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 2.5 ns | — |
| Maximum Internal Frequency | 250 MHz (-1V speed grade) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| LVDS Support | Yes | Yes |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 °C | — |
| Qualification | Not Qualified | — |
| Programming Interface | IEEE 1532 / JTAG | — |
| Number of Logic Elements | — | 16640 |
| Number of Logic Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Total RAM Bits | — | 212992 |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | — | 2.5 V (LVDS-capable) |
| Maximum Operating Frequency | — | 200 MHz |
| Propagation Delay (Tpd) | — | 3.1 ns |
| Boîtier / Format | — | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | — | 655-CPGA, 62.48 x 62.48 mm |
| Température de fonctionnement | — | Industrial (per Altera part-number -N suffix) |
| Type de montage | — | Through-Hole (CPGA, socket-compatible) |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | — | JTAG / Passive Serial |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |