EP20K400GC655-2X vs EP20K400GC655-2N Comparison
Detailed side-by-side comparison of EP20K400GC655-2X by Altera and EP20K400GC655-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-2X | EP20K400GC655-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $127.50 |
| Family | APEX 20K | APEX 20KC |
| Series | APEX-20KCยฎ | โ |
| Logic Elements / Cells | 16640 | โ |
| System Gates | 400000 | โ |
| Total RAM Bits | 212992 | 212992 |
| Number of I/O | 496 | [DATA_NEEDED: I/O count] |
| Number of Dedicated Inputs | 6 | โ |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | [DATA_NEEDED: LAB count] |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | โ |
| Maximum Operating Frequency | 200 MHz | 200 MHz |
| Process Technology | 0.22 ยตm CMOS | 0.22 ยตm CMOS |
| Core Supply Voltage | 2.5 V | โ |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | โ |
| Package Type | 655-BCPGA (SPGA655) | โ |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | โ |
| Package Dimensions | 47 x 47 mm | โ |
| Peak Reflow Temperature | 220 ยฐC | โ |
| Mounting Type | Through-hole (CPGA) | Through-Hole (CPGA, socket-compatible) |
| Programmability | In-system, JTAG (IEEE 1149.1) | โ |
| Operating Temperature | [DATA_NEEDED: temperature grade] | Industrial (per Altera part-number -N suffix) |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Number of Logic Elements | โ | 16640 |
| Number of Logic Cells | โ | 16640 |
| Total System Gates | โ | 400000 |
| Core Voltage (VCCINT) | โ | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | โ | 2.5 V (LVDS-capable) |
| Propagation Delay (Tpd) | โ | 3.1 ns |
| Package / Case | โ | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | โ | 655-CPGA, 62.48 x 62.48 mm |
| LVDS Support | โ | Yes |
| Architecture | โ | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | โ | JTAG / Passive Serial |
| MSL Level | โ | [DATA_NEEDED: MSL level] |