EP20K400GC655-2X vs EP20K400GC655-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2X sa pamamagitan ng Altera at EP20K400GC655-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GC655-2X | EP20K400GC655-2N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC |
| Series | APEX-20KC® | — |
| Logic Elements / Cells | 16640 | — |
| System Gates | 400000 | — |
| Total RAM Bits | 212992 | 212992 |
| Number of I/O | 496 | [DATA_NEEDED: I/O count] |
| Number of Dedicated Inputs | 6 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | [DATA_NEEDED: LAB count] |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Maximum Operating Frequency | 200 MHz | 200 MHz |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | — |
| Package Type | 655-BCPGA (SPGA655) | — |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | — |
| Package Dimensions | 47 x 47 mm | — |
| Peak Reflow Temperature | 220 °C | — |
| Uri ng Pagpapasok | Through-hole (CPGA) | Through-Hole (CPGA, socket-compatible) |
| Programmability | In-system, JTAG (IEEE 1149.1) | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | Industrial (per Altera part-number -N suffix) |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Number of Logic Elements | — | 16640 |
| Number of Logic Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | — | 2.5 V (LVDS-capable) |
| Propagation Delay (Tpd) | — | 3.1 ns |
| Packhaging / Kaso | — | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | — | 655-CPGA, 62.48 x 62.48 mm |
| LVDS Support | — | Yes |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| Configuration Method | — | JTAG / Passive Serial |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |