EP20K400GI655-1X vs EP20K400GC655-2X Comparison

Detailed side-by-side comparison of EP20K400GI655-1X by Altera and EP20K400GC655-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400GI655-1X EP20K400GC655-2X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family APEX 20K APEX 20K
Device EP20K400 —
Logic Elements 16640 —
Number of Terminals 655 —
User I/O Lines 502 —
Dedicated Inputs 4 —
Package Type Ceramic Pin Grid Array (CPGA) 655-BCPGA (SPGA655)
Package Code (JESD-30) S-CPGA-P655 —
Package Equivalence Code SPGA655,47X47 —
Package Body Material CERAMIC (metal-sealed co-fired) CERAMIC, metal-sealed cofired grid array
Speed Grade -1 —
Propagation Delay 2.5 ns (typical for -1 grade) —
Process Technology CMOS, SRAM-based configuration 0.22 µm CMOS
Moisture Sensitivity Level (MSL) 1 —
Peak Reflow Temperature 220 C 220 °C
Operating Temperature -40 C to +85 C (industrial) [DATA_NEEDED: temperature grade]
Mounting Type Through-Hole (PGA) Through-hole (CPGA)
RoHS Status Compliant unknown
Series — APEX-20KC®
Logic Elements / Cells — 16640
System Gates — 400000
Total RAM Bits — 212992
Number of I/O — 496
Number of Dedicated Inputs — 6
Number of LABs/CLBs — [DATA_NEEDED: number of Logic Array Blocks]
Number of EABs — [DATA_NEEDED: number of Embedded Array Blocks]
Maximum Operating Frequency — 200 MHz
Core Supply Voltage — 2.5 V
I/O Supply Voltage (MultiVolt) — 2.5 V / 3.3 V / 5 V
Package Dimensions — 47 x 47 mm
Programmability — In-system, JTAG (IEEE 1149.1)

Datasheets & Resources

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