EP20K400GI655-2 vs EP20K400GC655-2N Comparison
Detailed side-by-side comparison of EP20K400GI655-2 by Altera and EP20K400GC655-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-2 | EP20K400GC655-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $127.50 |
| Manufacturer | Altera Corporation | β |
| Series | APEX 20K (EP20K400) | β |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Typical Gate Count | 400,000 gates | β |
| Logic Elements (LE) | 16,640 | β |
| Maximum User I/O | 496 | β |
| Dedicated Inputs | 6 | β |
| Number of Terminals | 655 | β |
| Package | SPGA-655 (47 mm x 47 mm) | β |
| Nominal Supply Voltage | 2.5 V | β |
| Supply Voltage Range | 2.375 V to 2.625 V | β |
| Propagation Delay | 3.1 ns (typical) | β |
| Technology | CMOS SRAM | β |
| Operating Temperature | -40C to +85C (industrial) | Industrial (per Altera part-number -N suffix) |
| Mounting Type | Through-Hole / Socket | Through-Hole (CPGA, socket-compatible) |
| Moisture Sensitivity Level | 1 (per Altera family) | β |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | JTAG / Passive Serial |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | β |
| Embedded Memory | Embedded System Blocks (ESBs) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | Obsolete (legacy Altera APEX 20K family) | β |
| Family | β | APEX 20KC |
| Number of Logic Elements | β | 16640 |
| Number of Logic Cells | β | 16640 |
| Total System Gates | β | 400000 |
| Total RAM Bits | β | 212992 |
| Number of I/O | β | [DATA_NEEDED: I/O count] |
| Number of LABs/CLBs | β | [DATA_NEEDED: LAB count] |
| Core Voltage (VCCINT) | β | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | β | 2.5 V (LVDS-capable) |
| Process Technology | β | 0.22 Β΅m CMOS |
| Maximum Operating Frequency | β | 200 MHz |
| Propagation Delay (Tpd) | β | 3.1 ns |
| Package / Case | β | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | β | 655-CPGA, 62.48 x 62.48 mm |
| LVDS Support | β | Yes |
| Architecture | β | MultiCore (LUT + product-term + embedded memory) |
| MSL Level | β | [DATA_NEEDED: MSL level] |