EP20K400GI655-2 vs EP20K400GC655-2N 对比

详细并排对比 EP20K400GI655-2 出自 Altera 和 EP20K400GC655-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400GI655-2 EP20K400GC655-2N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $175.00 $127.50
Manufacturer Altera Corporation —
Series APEX 20K (EP20K400) —
Device Type Field Programmable Gate Array (FPGA) —
Typical Gate Count 400,000 gates —
Logic Elements (LE) 16,640 —
Maximum User I/O 496 —
Dedicated Inputs 6 —
Number of Terminals 655 —
封装 SPGA-655 (47 mm x 47 mm) —
Nominal Supply Voltage 2.5 V —
Supply Voltage Range 2.375 V to 2.625 V —
Propagation Delay 3.1 ns (typical) —
Technology CMOS SRAM —
工作温度 -40C to +85C (industrial) Industrial (per Altera part-number -N suffix)
安装类型 Through-Hole / Socket Through-Hole (CPGA, socket-compatible)
Moisture Sensitivity Level 1 (per Altera family) —
Configuration Method JTAG, Passive Serial, Passive Parallel JTAG / Passive Serial
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+ —
Embedded Memory Embedded System Blocks (ESBs) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
生命周期状态 Obsolete (legacy Altera APEX 20K family) —
Family — APEX 20KC
Number of Logic Elements — 16640
Number of Logic Cells — 16640
Total System Gates — 400000
Total RAM Bits — 212992
Number of I/O — [DATA_NEEDED: I/O count]
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Core Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Voltage (VCCIO) — 2.5 V (LVDS-capable)
Process Technology — 0.22 µm CMOS
Maximum Operating Frequency — 200 MHz
Propagation Delay (Tpd) — 3.1 ns
封装 / 外壳 — 655-BCPGA (Ceramic Pin Grid Array)
Supplier Device Package — 655-CPGA, 62.48 x 62.48 mm
LVDS Support — Yes
Architecture — MultiCore (LUT + product-term + embedded memory)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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