EP20K400GI655-3V vs EP20K400GC655-2V Comparison
Detailed side-by-side comparison of EP20K400GI655-3V by Intel and EP20K400GC655-2V by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GI655-3V - APEX 20K 400K-Gate FPGA, 16K LE, 655-Pin PGA | Altera (Intel)
EP20K400GI655-3V ObsoleteAltera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V β Last Time BuySpecification Comparison
| Parameter | EP20K400GI655-3V | EP20K400GC655-2V |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $142.50 | $92.75 |
| Series | APEX 20K | APEX-20KC |
| Device Family | EP20K400 | β |
| Logic Elements | 16,640 | 16,640 |
| Typical Gate Count | 400,000 gates | β |
| Maximum User I/O | 496 | β |
| Dedicated Inputs | 6 | β |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | β |
| Total Embedded RAM | [DATA_NEEDED: total RAM bits] | β |
| Technology | CMOS (0.18 Β΅m process) | β |
| Maximum Internal Clock Frequency | 714.2 MHz | β |
| Supply Voltage VCCINT | 2.5 V | β |
| I/O Supply Voltage VCCIO | 2.5 V or 3.3 V | β |
| Package | 655-pin SPGA (Staggered PGA), 47 x 47 mm | 655-CPGA (62.48 x 62.48 mm) |
| Mounting Type | Through-Hole (Pin Grid Array) | Through-hole (CPGA) |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial) | [DATA_NEEDED: temperature grade] |
| Moisture Sensitivity Level (MSL) | 1 | β |
| Qualification | Not Qualified | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Configuration Interface | IEEE 1149.1 JTAG + serial / parallel passive | β |
| Family | β | APEX 20KC (1.8 V, LVDS) |
| Total RAM Bits | β | 212,992 |
| System Gates | β | ~400,000 (typical marketing figure) |
| Number of I/O | β | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | β | 2.375 V to 2.625 V (nominal 2.5 V) |
| Propagation Delay | β | 3.000 ns |
| Process Technology | β | CMOS, 0.18 um |
| LVDS Support | β | Yes |
| Package Type | β | Ceramic Pin Grid Array, through-hole |
| Speed Grade | β | -2 |
| Lead-Free | β | unknown |
| Architecture | β | MultiCore (LUT + product-term + embedded memory) |