EP20K600CF33C9 vs EP20K600CF33C8 Comparison
Detailed side-by-side comparison of EP20K600CF33C9 by Intel and EP20K600CF33C8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF33C9 | EP20K600CF33C8 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $171.00 | $285.75 |
| Family | APEX 20KC | APEX 20KC |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS |
| System Gates | 600,000 (maximum) | β |
| Logic Elements / Cells | 24,320 | β |
| Maximum Operating Frequency | 250 MHz | β |
| Maximum Clock Frequency | 303.03 MHz | β |
| Propagation Delay | 2.0 ns | β |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | β |
| User I/O | 588 (4 dedicated inputs + 580 general-purpose I/O) | β |
| Package | 1020-ball FC-FBGA | 1020-ball FineLine BGA (FC-FBGA), 33 x 33 mm |
| Mounting Type | Surface Mount (BGA) | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| Embedded RAM | Dual-port RAM blocks (per family) | β |
| Programmability | JTAG / IEEE 1149.1 ISP, SRAM-based | β |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant (lead-free version) / non-compliant for legacy C-speed grade variant |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Logic Block Architecture | MultiCore (LUT + product-term + embedded memory) | β |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS (per family datasheet) | β |
| Device Type | β | FPGA (Field Programmable Gate Array) |
| Typical Gates | β | 600,000 |
| Logic Elements | β | 24,320 |
| Embedded RAM Bits | β | 311,296 |
| Embedded System Blocks (ESB) | β | 152 |
| Maximum User I/O | β | 488 |
| Core Voltage (VCCINT) | β | 1.8 V |
| I/O Voltage (VCCIO) | β | 1.8 V / 2.5 V / 3.3 V (bank-selectable) |
| LVDS Support | β | Yes, up to 840 Mbps |
| PLLs | β | 4 enhanced PLLs |
| Speed Grade | β | -8 |
| Operating Temperature | β | Commercial (0 Β°C to +85 Β°C) |
| Configuration Modes | β | Passive Serial, Passive Parallel Asynchronous, Passive Parallel Synchronous, JTAG |
| Status | β | NRND / Last-Time-Buy (per Altera/Intel product notice) |