EP20K600CF672-1X vs EP20K600CF672-3 Comparison

Detailed side-by-side comparison of EP20K600CF672-1X by Intel and EP20K600CF672-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672-1X EP20K600CF672-3
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Series APEX 20KC —
Device Family APEX 20KC MultiCore FPGA —
Maximum Typical Gates 600,000 —
Logic Elements 31,104 (per Altera APEX 20KC datasheet family) —
Embedded System Blocks (ESBs) up to 256 —
Embedded Memory (max bits) [DATA_NEEDED: ESB RAM bits] —
PLLs 4 4
Maximum User I/O [DATA_NEEDED: max user I/O count] —
Package 672-ball BGA (CF672), 1.27 mm pitch 672-ball FineLine BGA
Speed Grade -1 (industrial speed grade, X = lead-free) -3
Process Technology 0.18 um SRAM CMOS 0.18 µm CMOS
Configuration Method SRAM, JTAG (IEEE 1149.1), EPC passive serial —
Supply Voltage [DATA_NEEDED: VCCINT/VCCIO] —
Operating Temperature [DATA_NEEDED: industrial temp range] [DATA_NEEDED: operating temperature range]
Mounting Type Surface Mount (BGA) Surface Mount
MSL Level [DATA_NEEDED: MSL rating] —
RoHS Status Compliant (per Alibaba distributor listing: "RoHS Compliant") Lead-free / RoHS compliant (per Alibaba listing)
Family — APEX 20KC
Typical Gates — 600,000
Maximum System Gates — 2,432,000
Maximum Logic Elements — 2,432
Embedded System Memory — 311,040 bits (380 Kbits ESB)
User I/O Pins — 488
Maximum Internal Frequency — 180 MHz (per APEX 20K family datasheet)
Configuration Modes — PS, PPS, PPA, JTAG, EPC2/EPC16
I/O Standards Supported — LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI

Datasheets & Resources

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