EP20K600CF672 vs EP20K600CF672-2 Comparison

Detailed side-by-side comparison of EP20K600CF672 by Intel and EP20K600CF672-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP20K600CF672 EP20K600CF672 - 600K APEX 20KC FPGA, 672-BGA | Intel

EP20K600CF672 - 600K APEX 20KC FPGA, 672-BGA | Intel

EP20K600CF672 [data_needed: lifecycle status]

Specification Comparison

Parameter EP20K600CF672 EP20K600CF672-2
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status [DATA_NEEDED: lifecycle status] Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $680.00
Product Type Field-Programmable Gate Array (FPGA) β€”
Product Family APEX-20KC β€”
Manufacturer Altera / Intel Intel / Altera
User I/O Lines 508 I/O β€”
Logic Elements [DATA_NEEDED: logic element count] 30,720
Propagation Delay 1.48 ns for supplied EP20K600CF672C9N/C8N references β€”
Device Type Listed by Supplied References SPLD β€”
Process Technology 0.15 um all-layer copper-metal process for supplied family references 0.18 um CMOS
Performance Claim Up to 35% faster than APEX 20KE devices β€”
Package Type 672-ball BGA, FCBGA 672-ball FineLine BGA (FCBGA)
Package Dimensions 45 mm x 45 mm β€”
Ball Pitch 1.27 mm β€”
Mounting Type Surface Mount Surface Mount
Operating Temperature 0 C to 85 C for supplied EP20K600CF672C9N/C8N references 0 C to +60 C (TJ, per Alibaba supplier listing)
Configuration Device Type Enhanced Configuration (EPC) device β€”
Core Voltage [DATA_NEEDED: core supply voltage] β€”
I/O Voltage [DATA_NEEDED: I/O supply voltage] β€”
Configuration Memory [DATA_NEEDED: configuration memory type and capacity] β€”
Embedded Memory [DATA_NEEDED: embedded memory capacity] β€”
RoHS Status unknown [DATA_NEEDED: rohs_status]
REACH Status unknown β€”
AEC-Q100 Status unknown β€”
Series β€” APEX 20KC
Device Family β€” APEX 20KC PLD
Gate Count (typical) β€” 600,000 gates
Embedded RAM (approx.) β€” 311,232 bits
Speed Grade β€” -2
Configuration Mode β€” Enhanced Configuration (EPC)
Number of PLLs β€” 4
I/O Standards β€” LVTTL, LVCMOS, and others per datasheet
Boundary Scan β€” IEEE 1149.1 (JTAG)
Lifecycle Status β€” Obsolete / last-time-buy

Datasheets & Resources

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