EP20K600CF672 vs EP20K600CF672-2 比較
詳細な並列比較: EP20K600CF672 メーカー: Intel および EP20K600CF672-2 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP20K600CF672 - 600K APEX 20KC FPGA, 672-BGA | Intel
EP20K600CF672 [data_needed: lifecycle status]
仕様比較
| パラメータ | EP20K600CF672 | EP20K600CF672-2 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | [DATA NEEDED: Lifecycle Status] | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $680.00 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Product Family | APEX-20KC | — |
| Manufacturer | Altera / Intel | Intel / Altera |
| User I/O Lines | 508 I/O | — |
| Logic Elements | [DATA_NEEDED: logic element count] | 30,720 |
| Propagation Delay | 1.48 ns for supplied EP20K600CF672C9N/C8N references | — |
| Device Type Listed by Supplied References | SPLD | — |
| Process Technology | 0.15 um all-layer copper-metal process for supplied family references | 0.18 um CMOS |
| Performance Claim | Up to 35% faster than APEX 20KE devices | — |
| Package Type | 672-ball BGA, FCBGA | 672-ball FineLine BGA (FCBGA) |
| Package Dimensions | 45 mm x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0 C to 85 C for supplied EP20K600CF672C9N/C8N references | 0 C to +60 C (TJ, per Alibaba supplier listing) |
| Configuration Device Type | Enhanced Configuration (EPC) device | — |
| Core Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory type and capacity] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | — |
| RoHS ステータス | unknown | [DATA_NEEDED: rohs_status] |
| REACH Status | unknown | — |
| AEC-Q100 Status | unknown | — |
| Series | — | APEX 20KC |
| Device Family | — | APEX 20KC PLD |
| Gate Count (typical) | — | 600,000 gates |
| Embedded RAM (approx.) | — | 311,232 bits |
| Speed Grade | — | -2 |
| Configuration Mode | — | Enhanced Configuration (EPC) |
| Number of PLLs | — | 4 |
| I/O Standards | — | LVTTL, LVCMOS, and others per datasheet |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| ライフサイクル状態 | — | Obsolete / last-time-buy |