EP20K60EFC144-2X vs EP20K60EFC144-2XN Comparison

Detailed side-by-side comparison of EP20K60EFC144-2X by Altera and EP20K60EFC144-2XN by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K60EFC144-2X EP20K60EFC144-2XN
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family APEX-20KE APEX-20K (MultiCore Architecture)
Logic Elements 2,560 —
Typical Gates 60,000 —
Embedded RAM Bits 32,768 —
User I/Os 93 —
Number of PLLs 4 —
Package 144-pin FBGA (13x13 mm) —
Process Technology 0.22 µm CMOS —
Core Voltage 1.8 V (1.71 V – 1.89 V) —
Operating Temperature 0 °C to +85 °C (commercial) —
Mounting Type Surface Mount Surface Mount
RoHS Status Unknown (legacy part - check distributor) [DATA_NEEDED: RoHS status]
Configuration SRAM-based, JTAG (IEEE 1149.1) —
Speed Grade -2 (faster commercial) -2 (per MPN suffix)
Tool Support Quartus II, MAX+PLUS II —
Series — APEX-20KE
Typical Gate Count — 60,000 gates
Logic Elements / Embedded Array Blocks — 2,560
Embedded Memory (Bits) — 32,768
Maximum User I/O — 93
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Core Supply Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Supply Voltage (VCCIO) — [DATA_NEEDED: VCCIO range]
Package Type — 144-BGA (Fine-pitch Ball Grid Array)
Package Code (per MPN suffix) — FBGA / LBGA, 13x13 mm
Operating Temperature (TJ) — 0 C to +85 C (commercial)
Configuration Method — JTAG (IEEE 1149.1), Passive Serial, Parallel
Logic Family — CMOS, SRAM-based LUT

Datasheets & Resources

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