EP20K60EFC144-2X vs EP20K60EFC144-2XN Comparación
Comparación detallada lado a lado de EP20K60EFC144-2X por Altera y EP20K60EFC144-2XN por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN NrndComparación de especificaciones
| Parámetro | EP20K60EFC144-2X | EP20K60EFC144-2XN |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $42,65 | $152,00 |
| Family | APEX-20KE | APEX-20K (MultiCore Architecture) |
| Logic Elements | 2,560 | — |
| Typical Gates | 60,000 | — |
| Embedded RAM Bits | 32,768 | — |
| User I/Os | 93 | — |
| Number of PLLs | 4 | — |
| Encapsulado | 144-pin FBGA (13x13 mm) | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Voltage | 1.8 V (1.71 V – 1.89 V) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (commercial) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | Unknown (legacy part - check distributor) | [DATA_NEEDED: RoHS status] |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) | — |
| Speed Grade | -2 (faster commercial) | -2 (per MPN suffix) |
| Tool Support | Quartus II, MAX+PLUS II | — |
| Series | — | APEX-20KE |
| Typical Gate Count | — | 60,000 gates |
| Logic Elements / Embedded Array Blocks | — | 2,560 |
| Embedded Memory (Bits) | — | 32,768 |
| Maximum User I/O | — | 93 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Package Type | — | 144-BGA (Fine-pitch Ball Grid Array) |
| Package Code (per MPN suffix) | — | FBGA / LBGA, 13x13 mm |
| Operating Temperature (TJ) | — | 0 C to +85 C (commercial) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Parallel |
| Logic Family | — | CMOS, SRAM-based LUT |